Currently I am using FPGA to develop AD7760, first put the data in sram (IS61WV102416ALL), and then sent to the computer via usb, but the data recurrence,why?
According to the AD7760 data sheet，，
Combined with the relationship between signal to noise ratio and bit number，
By calculation, the AD7760 did not really reach 24 bits,I would like to know what circumstances can achieve 24 bits？Did i understand…
I'm interfaceing an AD7760 to an FPGA and I experienced that, during setting a configuration register resp. reading status registers, the ADC is signaling ADC-results by pulling DRDY low. Is there no arbitration? In the output stream Status…
When using the AD7760 Evaluation board. Let the customer power up the AD7760 Evaluation board first, with correct supply, 7.5V on J2 of the eval board. When the board is powered up and connected, the AD7760 evaluation software can be launch…
thanks for reply ,
in ad7760 what type of three filter is? and which is user defined?
i don't familiar with matlab.any other software that can i calculate filter coefficient for ad7760.
any exelsheet for ad7760 same to AD7785/92/ 93/ 94/ 95…
Hi Fausto bartra.
You can download the software for EVAL-AD7760/62EDZ provided in this link: AD7760 Evaluation board.
Thanks and Best Regards,
Hello AD forums,
I have a question that I hope one of you may be able to help with ...
I have an AD7760 evaluation board (eval-ad7760) and would like to know if there's some kind of input over-voltage protection on this board ... I've looked at the…
On the current GUI of the AD7760 evaluation board, the CDIV value cannot be change. The default value is CDIV=0, which is ICLK = MCLK/2. The only way would be to write to the control register of AD7760.
Based on the key ADC specifications you have offered, it would appear like the AD7760 is the closest solution I can point you towards: www.analog.com/AD7760
I hope that helps.