• AD7682 Interface Timing

    I am using the AD7682 in Read/Write Spanning Conversion mode without busy indicator (page 34 of datasheet). It mentions in this section that the first 15 SCK falling edges clock out the conversion results starting with MSB – 1. However, the timing…

  • AD7682: FAQ

    FAQ

  • AD7682 and AD7688 busy indicator

    Q 

    1.
    I am using AD7682 and AD7688 components. I do accesses through a PLD and I am
    wondering how using the busy indicator.

    In the AD7682 datasheet, in the paragraph "General timing with a busy
    indicator", it is written: "At the EOC, if CNV…

  • AD7682 SAR ADC Design considerations

    I'm going to use the AD7682 SAR ADC for my design, this is an excellent device that is small and has the ability to scale the power with throughput. Is there anything I should consider for my design. 

  • AD7682 - Non linear response using internal reference.

    Hi, 

    The ADC configuration is as follows,

    • CFG = 1. // Overwrite content.
    • INCC = 000. // Bipolar differential pairs; INx− referenced to VREF/2 ± 0.1 V.
    • INx = 000. // IN0 (IN0+) and IN1 (IN0-) enabled.
    • BW = 0. // ¼ BW
    • REF = 000. // Internal…

  • RE: AD7682 control from FPGA logic (not NIOS)

    Ivor,

    No worries.  With response to your queries.

    1) I believe you meant to type the configuration word was 0xF614 and this appears to be correct from your timing.

    Ivor said:
    1. My configuration word is set to be 0xF316 as suggested by you the last time…

  • RE: AD7682 temperature sensor

    JPantoja,

    The nominal value of the temperature sensor is not trimmed NOR is it guaranteed as it is only listed as a typical value (no Max/Min Range) thus there is no errata here.  Therefore the temperature measurement function should only be used as a…

  • AD7682 READ/WRITE SPANNING CONVERSION WITH A BUSY INDICATOR timing diagram

    I AD7682 datasheet at page 35, there is a timing diagram(figure.45) for READ/WRITE SPANNING CONVERSION WITH A BUSY INDICATOR.

    In this diagram, SCLK has idle high setting and the fast falling edge  shifts out MSB data. But it has 17 more clocking.

    I think…

  • AD7682/7689 SPI parallel connection

    Hi,

    The AD7682/AD7689 does not have a CS pin, but does it support multiple devices with SPI parallel connection?

    While the CNV/ pin is set to high, the SDI input is invalid and the SDO becomes high impedance.

    So I think that if CNV/ pin keep high after…

  • RE: AD7682

    Blaider,

    There are a couple of things I would point out to you.

    1) Note that because you only execute a single conversion to load the configuration data into the part the actual configuration does not change until the third sample you take in each 5 sample…