• AD7663: FAQ

    FAQ

  • AD7663: PCB layout

    Q 

    We are now trying to design a PCB for the three AD7633s and associated
    circuitry. Our customer has asked us to look at your reference design as
    detailed in document, EVAL-AD76XXCBZ. However, I would like to ask you (or your
    colleagues) about the…

  • AD7663 Substitute?

    What is a good substitute for IC AD7663?  

  • RE: AD7663

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    …

  • RE: AD7663 doesn't work in a custom board

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  • AD7663转换的数据为0

    使用STM32F4与AD7663通信，无论采用CPU自带的SPI口还是自己用普通IO口去读AD7663的数据，读出的结果都是0。采用AD7663的BUSY下降沿作为中断，可正常进入中断。用普通IO口模拟的时钟时序没问题。电路图和部分程序如下，求大神指教。

    电路：

    部分程序：

    1、AD7663初始化

    //连接AD7663的IO口初始化

    void AD7663_IO_Init( void )

    {

        GPIO_InitTypeDef  GPIO_InitStructure;

        RCC_AHB1PeriphClockCmd…

  • RE: AD7663 - External Discontinuous Clock Data Read after Conversion

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  • AD7663模拟输入范围不满足设置需求

    AD7663ASTZ芯片模拟输入范围不满足要求。我们配置了模拟输入范围为±5V，可是通过测试发现模拟输入信号范围为±2.5V，当超过2.5V时，无法输出正确采样结果，电路配置如图。输入幅度2.5V正弦信号时，最大采样结果为31600，接近满量程。

  • AD7663并口采集，一次CNVST信号触发BUSY信号多次。

    如题，我设计32K采样率，PD、CS、RD均拉低，用示波器看CNVST信号没错。但是BUSY信号抬高多次。如图。大周期与CNVST周期吻合。

  • AD7663使用两路采集信号的时序问题

    本人使用AD7663两路同时采集信号，将两路的信号交给FPGA做处理，由于数据总线只有一组，而且我看了下手册没有讲述时序区别这两路的信号，请问我怎样才能区分开两路的数据，达到FPGA分别处理的目的？