• AD7380-4

    AD7380-4 is a 16-bit compatible,quad,simultaneous sampling,high speed,successive approximation register(SAR), analog-to-digital converters(ADC),how to control multi AD7380-4 simultaneous sampling by FPGA?

  • FAQ(AD7380): The AD7380(AD738x family) ADC has an on-chip buffered 2.5V reference. Can this internal reference be use to supply external circuitry?

    The buffered 2.5V internal reference of the AD7380 is recommended to use for internal circuitry process. When this on-chip 2.5V reference is use for external circuit, it must be connected to an external buffer amplifier for example the ADA4807. The external…

  • AD7380/AD738x 80Mhz SCLK frequency

    Q

    The AD7380/AD738x datasheet uses the 80Mhz SCLK frequency. Can a lower frequency be used in the communication interface?

    A

    AD738x has a throughput rate of 4MSPS.  Faster SCLK frequency enables to achieve a higher throughput rate.  The 80Mhz SCLK freq…

  • AD7380 SNR at higher input frequencies?

    Hi,

    In the AD7380 datasheet (Figure 18) the SNR vs input frequency rolls off and there is no data provided above ~100 kHz. Is there a reason for this?

    What kind of SNR could one expect for a signal at 1 or 2 MHz?

    Thanks,

    Christer

  • RE: AD7380 推荐的MCU

    AD7380对CS信号有要求。一些ST芯片的SPI的硬件CS信号不支持同步数据帧的功能。

  • Ad7380 adc data reading issue

    Hi ,

    we are using Ad7380 in 2 wire mode.

    with 2 wire mode configuration ,we are able to see the output sine ,square and ramp  waveform  on iio scope with some glitches on upper and lower edges. we tried configuring the vref on device tree…

  • AD7380 family Alert function and setting alert threshold

    Q

    The AD7380/AD738x family of generics has an Alert feature.. The limits are set in the  Alert threshold register. Can the Alert threshold limit be set per channel?

    A

    The alert threshold low and alert threshold high is set in the Alert Threshold Low register…

  • AD7380 data rate

    The AD7380 datasheet specifies that the data rate is 4MSPS. However, the diagram on page 7 appears to show a data rate of 8 MSPS when in "serial 2-wire" mode.

    Is the 4 MSPS specification for a single ADC or for both ADCs together? What is the…

  • The AD7380(AD738x) a 16-bit resolution ADC throughput rate is at 4MSPS. When resolution boost is enable allowing 18-bit conversion result. With the additional 2-bits, does the AD7380 would still able to maintain the throughput rate at 4MSPS?

    The AD7380 is capable to perform with throughput rates over 4MSPS using the correct SCLK at 80 Mhz frequency. When the normal averaging oversampling and resolution boost are enabled, the throughput rate will slow down as the oversampling ratio increases…