• FAQ(AD7380): The AD7380(AD738x) a 16-bit resolution ADC throughput rate is at 4MSPS. When resolution boost is enable allowing 18-bit conversion result. With the additional 2-bits, does the AD7380 would still able to maintain the throughput rate at 4MSPS...

    The AD7380 is capable to perform with throughput rates over 4MSPS using the correct SCLK at 80 Mhz frequency. When the normal averaging oversampling and resolution boost are enabled, the throughput rate will slow down as the oversampling ratio increases…

  • FAQ(AD7380): The AD7380(AD738x family) ADC has an on-chip buffered 2.5V reference. Can this internal reference be use to supply external circuitry?

    The buffered 2.5V internal reference of the AD7380 is recommended to use for internal circuitry process. When this on-chip 2.5V reference is use for external circuit, it must be connected to an external buffer amplifier for example the ADA4807. The external…

  • RE: AD7380 eval board performance

    Hello Jonathan,

    As per your suggestion in below linked thread we have used the analog filter(capacitor based) in the setup.

    https://ez.analog.com/data_converters/precision_adcs/f/q-a/536556/analog-filter-used-before-ad7380-evm

    Setups are given below…

  • RE: AD7380 Analog Input Range

    Hello Kommissar,

         Do you have a power-up sequence on your application? Looking into the Abs max rating of the AD7380, the REFIO pin range is related to the VCC. Violation on this abs max rating could potentially damage the part. I good power up and power…

  • AD7380: FAQs

    Question:

    The AD7380 has an on chip oversampling, Why is there a need for an oversampling?

    Answer:

    Oversampling has been a known method of processing conversion result to improve ADC performance for SAR ADC. Putting the oversampling process internally…

  • RE: AD7380 SPI Settings

    Hi,

        For the AD7380, conversion data, MSB is shift out as soon as the CS goes low, the subsequent data bits are shift out at the rising edge of SCLK,. Based from this figure , the recommended SPI timing would be CPOL=1 and CPHA = 0.

    Regards,

    Jonatha…

  • Analog Filter used before AD7380 EVM

    Hello,

    In AD7380 EVM user guide one analog filter has been used (Mentioned in the first page of user guide UG-1304)

    1) Kindly share details of the analog filter.

    2) Also the signal characteristics used to get result as given in figure 20 of user guide…

  • An optimal ADC driver for AD7380/AD7381?

    Dear ADI,

    We are planning to use AD7380/AD7381 in our products, sensing two industrial signal (+- 13.5V) simultaneously. We now stop on the choices of ADC drivers.

    In the past, we are using CN0385 (AD8251 + AD8475 + AD4003) as the solution, and in using…

  • ADC Driver Low noise for AD7380

    Hi,

        I checking on other ADC Driver. I ma currently using ADA4945, ADA4896 and ADA4807. Are there other recommended new ADC drivers for AD7380?

    Regards,

    Jocs

  • AD7380 : SCLK for 2-wire mode

    Hello,

    I'm DFAE in Japan. I have a question about SCLK in 2-wire mode of AD7380 from a customer.

    I think we don't need to send SCLK while SDOA/SDOB are DON'T CARE. Is it correct?

    Best Regards,

    Akira