• Does EVAL-AD7357 requires pull-up resistor for the SDATA and SCLK?

    Hi, I had an EVAL-AD7357 and I faced the problem that the output signal from the SDATA pin cannot meet the threshold level. 

    Is the pull-up resistor is required for this eval board? 

    The yellow color signal is SCLK while the blue color signal is for SDATA…

  • RE: AD7357 can be usd to Single ended input?

    Hi,

    AD7375 is designed to have differential input signals. My suggestion is you can use a single-ended to differential amplifier ADC driver such as AD4945-1 to adapt to your application.

    Regards,

    Andrei

  • AD7357 power mode

    HI,

    in power mode , it was mentioned that in first time  a few cycle has to be elapsed then only conversion start.

    1.But i my case i am using cs is low for 0.5usec, when cs is low sclk( each cycle frequequency 40Mhz) pulse start ,so conversion will start…

  • AD7357 power consumption

    Dear All,


    the question: is 36mW of power reported on the datasheet the total power consumption,

    I mean when the two channels are converting, or for just one channel?

    Thank You.

    Giuseppe

  • AD7357 output is not coming

    1.i am using this ADC7357 along with its driver8138ICin my design.but even though input signal  analog signal differential(60HZ),SCLK(40Mhz),CS(2Mhz) is coming on respective pins,but output is not showing.the output i am seeing in ILA of vivado tool.

  • RE: AD9837, AD8302, AD7357, 10-200kHz Impedance Analyzer

    hi,

    i am following same plan as given in overview.jpg 

    are you using AD8302 to calculate Z? and if yes then please can you explain the calculations of impedance using Vphs and Vmag

  • ad8138驱动AD7357,AD7357基准输出变为2.9V?

    采用AD8138驱动AD7357单端转差分,基准采用AD7357输出基准,原理图参考的AD7357参考设计,实际调试发现AD7357基准输出不正常,为2.9V,供电回路为正负5V,实测为4.9V和-4.7V。取下一片AD8138后对应回路的AD基准电压恢复正常,另外一路基准电压仍然是2.9V。请问是什么原因造成的。

  • AD7357 serial interface

    Hi guys,

    I'm currently using the AD7357 and I was wondering if I can pull up NCS (N for not) right after the 16th falling edge of SCKL or if I should wait the 16th rising edge of SCKL as shown on the picture 31 of the datasheet?

    Thanks in advanced…

  • RE: what is the minimum sampling rate of AD7357 adc

    HI sang@bel,

       The AD7357 data conversion process is initiated when CS goes low, this set the track and hold amplifier into hold mode. This samples the analog signal. at this point also the data bus is taken out of the three state which can now clock out…

  • AD7357的数据延迟问题

    您好!

    关于AD7357这款产品,文档中说AD7357的数据输出有一个采样周期的延迟。这个意思是说从第N次采样开始,到我能从AD7357得到第N次采样数据的时间间隔是一个采样周期?还是说从第N次采样结束,到我能从AD7357得到第N次采样数据的时间间隔是一个采样周期? 换句话说,像数据手册里Figure 30的图示,在采样的同时,实现数据的串行输出。那输出的数据是当前采样值还是上一个周期的采样值?

    谢谢!