• AD7323: output code

    In AD7323's datasheet, it says if the input is single-ended, then no missing
    code is 11-bit plus sign bit. I am not sure what the meaning is.  My question
    is:
    1. If the Input Range is 0~+10V and the coding is twos Complement, then when
    the…

  • RE: AD7323 DOUT ISSUE

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  • AD7323的输出码

    我的问题是:

    1. 如果输入范围是0~+10V,编码为二进制补码,那么当输入为0V时,符号位是什么,其余12位是什么?另外,当输入为+10V时,符号位是什么,其余12位是什么?

    2. 如果输入范围是-10V~+10V,编码为二进制补码,那么当输入为-10V时,符号位是什么,其余12位是什么?另外,当输入为+10V时,符号位是什么,其余12位是什么?

    Attachments:
  • RE: AD7323 output deviation with SPI frequency?

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • ad7323 DOUT valid

    Hi

    I am implementing a verilog component to interface to the ad7323 adc. I am having trouble figuring out when to sample DOUT in relation to the SCLK. Reading the timing diagram and Pin Function Descriptions confuses me.

    Based on the above description…

  • AD7323模数转换不准

    在使用AD7323的过程中,发现模数转换的结果不对,转换的数字量与输入的模拟量相差较大。用示波器看了下AD7323的输入端,发现在AD7323转化的过程中会出现较大的毛刺信号,放大毛刺信号,可以看到输入端发生明显的畸变。输入端前面是sallen key低通滤波电路,驱动能力比较强。后来在AD7323的输入端加了一个1uF的电容,毛刺信号明显削弱,模数转化结果误差减小。

  • AD7323 Decoupling

    Hello All,

    In the data sheet for the AD7323 it states: "Good decoupling is also important. All analog supplies should be decoupled with 10 μF tantalum capacitors in parallel with 0.1 μF capacitors to AGND....These low ESR, low ESI capacitors provide…

  • C software driver for the AD7323

    Does ADI provide a C software driver for the AD7323?

    Thanks,

    Mike