Hello,
I have questions about AD723.The start point of color burst from AD723 seems to move on AD723 Eval Board (AD723EB rev.B).Could you see attached file "Color_burst_AD723_rev01.xlsx" for more detail?
Thank you!
Best regards.Tamu
I am using AD723 from analog device in one of my design.
The above mentioned part is a analog RGB to NTSC/PAL converter.
Could anyone please let me know the acceptable input RGB resolution range for the part?
640 x 480
800 x 600
Etc..
My customer needs an RGB to PAL/NTSC converter. AD723 should be a good option but seems very old, Eval board working with DOS and win95... Is there a newer part? If no where can I find the design package for it?
Where can I find an updated schematic…
I am driving an AD723 with the output of a triple RGB DAC which is being driven by the digital RGB outputs of an LCD display driver. When I ramp the R, G and B outputs with test patterns, I see those colors go from dark to bright as expected. However…
I read in all of these datasheets that the AD723,AD725, and AD725 all require interlaced inputs. If I want to feed a pc's vga output into one of these IC's, would these still convert the RGB to composite? Are there other solutions from Analog Devices…
We are using DM388 SOC Display out which is connected to AD723 Encoder
What are the supported input resoltion for AD723?
We are Valitated the RGB out from DM388 to VGA conncetor it working fine.
The same RGB passed to AD723 for S-video conversion but…
Hi all.
We will have to design equipment with the AD723,Position of the burst signal of CVBS to be output is unstable.
Because 4FSC is provided only in AD723, It is running asynchronously to the source side RGB signal.
I need an explanation on how…
Are there any recommended xrandr or timing settings to use for a "NTSC-compatible" VGA 640x480 interlaced input video to the AD723?
I did this with AD7123 and AD723. It works. I even have implemented two oscillators to obtain PAL and NTSC and switch between them thru some logic. I used the composite sync from the AD7123 input, which I generate by the FPGA, also in a buffered form…