I'm working on AD7091R-8 evaluation board.
Currently I have enabled 3 channels out of 8.
I'm using the channel sequencer for reading the conversion results.
When I'm reading the conversion result of the enabled channels,I'm getting…
1. The absolute maximum on input current to any pin except supplies is +/-10mA(Please see page 7 of the AD7091R-8 data sheet)
2. Please see page 8 of the data sheet for description of the functions of the ADCIN and MUXOUT pins
I'm a DFAE in Japan. Our customer give us a question. There is a MOSFET inside SDA pin of AD7091R-5. On the other hand, is there NO MOSFET inside SCL pin of AD7091R-5? According to Table 5, we couldn't see Open-drain output about SCL as follows.…
The AD7091R-8 when in the channel sequencer mode, the conversion result of each channel has one conversion delay latency and the channel sequence start from the lowest channel to the highest channel. Figure 55, pp.36 of the datasheet shows…
I searched the git tree at GitHub - analogdevicesinc/no-OS: Software drivers for systems without OS for the no-OS driver for AD7091R-2/4/8 ADC and I couldn't find it there on any branch. There is a driver called AD7091R, but it doesn't support…
Thanks for your support.
We found that the issue is related to pulse width of CONVST. After achieving 500ns Pulse of CONVST, we are able to sample at every 1 uS interval.
I did send my question in this discussion:
As we are having similar issue. Basically initializing the ADC with 66 pulses of CONVST does not seem to work...
I can provide all probing or logging if needed.
The AD7997/98 I think would fit your requirement. You may also check the AD7291(8 channel) These uses I2C interface. There is need to configure the register to enable the channels that will be converted then reading the conversion result…
is there any simulation model for AD7091R ? I want to use a FPGA to connect to AD7091R to get data