You absolutely can read from channel 0 to channel 3 (1-4) in sequential order. Assuming you are using the AD7091R-4, you can simply program the channel register (ADDR = 0x01) with code 0x000F to enable channels 0 to 3 for conversion.
When reading the conversion result in the AD7091R-4, the MSB data is shifted on the falling edge of CS. The CS edge is needed, CS needs to high after 16th SCLK falling edge to return SDO high impedance.
Hi, Just to sync up.
I have placed a 100nF cap on the reset line and 100k to VDRIVE. This delays the rise time of the RESET line. So far I have not had any more issue at startup.
Let me check on this. Meanwhile, can you provide the configuration of the relevant links on your test? What did you use for 2.5V external reference? Also what external power supply unit was it that you used? We don't usually recommend using…
Unfortunately, we don't have it. At this moment, we are supporting AD7091R and AD7091R-5 (4 channels but I2C) - Linux Drivers [Analog Devices Wiki].
Now I'm designing my product by using AD7091R-4 and Altera FPGA.
I find the Altera FPGA's sample code for AD7091R on ADI wilki but it's only single channel and without controlling SDI pin.
So I would like to ask whether do you have…
Currently there is not an example device driver for this specific part. The AD7091 is close to the AD7091R-4, but it does not feature any of the configuration registers that are configured over the SPI interface. The only driver offered for…
I have a question , AD7091R-2,-4 External Reference Input range.
There is 1.0 - Vdd V in Page 3 , at dataseat
But , there is 2.5 - Vdd in Page 18 , at dataseat.
I think external reference input range is 1.0 - Vdd .
Which is correct?