Can anybody confirm if AD6676-EBZ will work with EVAL-TPG-ZYNQ3 ?

    Where I can find the information?



  • AD6676 Evaluation Board (EVAL-AD6676) - Help on SPI Control


    We are currently integrating the EVAL-AD6676 FMC Mezzanine with ZedBoard (Mini-ITX / Xilinx Zynq series) Evaluation platform.
    The EVAL-AD6676 was purchased through NISKO Projects / Israel.
    The SPI core is being implemented as…
  • AD6676 FAQ: Why isn't the noise floor of the AD6676 flat?

    I am looking at the noise spectral density (NSD) plots shown in NOMINAL PERFORMANCE characteristics of the datasheet and noticed that they are not flat and can vary depending on the AD6676 configuration.  Why?

    The AD6676 includes a tunable continuous…

  • AD6676 Internal Signal Processing Chain Related

    Inquiry about the scaling factor used within the signal processing chain within the AD6676.

    The data is available at the baseband output as shown in the figure (left one) but the GUI enabled with AD6676 evaluation board plots the spectrum in the bandpass…

  • AD6676 FAQ: Why are the performance specifications of the AD6676 different than the ones used to specify a typical ADC?

    I am familiar with typical ADC ac performance specifications such as SNR, SINAD, THD, SFDR, and ENOB when comparing ADC’s with each other. The AD6676 uses different specifications to quantify its ac performance characteristics. Why?

    Since the AD6676…

  • AD6676 FAQ: Why is the AD6676’s IF input resistance 60 ohms vs 50, 100 or even 200 ohms?

    While the design target was 50 ohms, device characterization for several lots has shown it to be closer to 60 ohms.  That said, operating with a low IF input resistance reduces PIN_0dBFS of the AD6676.  This in turn can reduce the P1dB requirements of…

  • AD6676 FAQ: What is the difference between a typical IF-sampling ADC and the AD6676 and why is called a Wideband IF Receiver Subsystem?

    An IF-sampling ADC typically refers to any ADC capable of digitizing an IF signal in its 2nd Nyquist zone (or higher) while still achieving sufficient dynamic range for the target application.   In a heterodyne or direct-sampling VHF receiver architecture…

  • AD6676 Configuration


    we are bringing up a board with one HMC7044 and one AD6676. Our goal is to set up a JESD204B/subclass 1 link between AD6676 and a JESD204B receiver placed in a FPGA. We have configured HMC7044 to generate the clock and the SYSREF signal to both the…

  • AD6676 driver


    There are FPGA reference designs for the AD6676 evaluation board. However I could not see any software drivers for it. Are there any plans regarding this? If so when is it going to be available roughly?



  • AD6676: DC offset


    We have a weather radar application using AD6676 as main digitizer. Our parameters are as follows:

    1. External clock: 100 MHz (so, using internal clock synthesizer)
    2. FADC = 3.2 GHz
    3. FIF = 75 MHz
    4. FIQ = 100 MHz
    5. Decimation: 32
    6. Coarse and fine QDDCs shift…