• AD6676 Samples Format in ADI JESD204B IP cores

    Hi, 

    Please let us know the JESD204B frame format for AD6676 for single and dual lane mode.

    Eg: I[0] Q[0],I[1] Q[1],etc.,

    In the AD RTL IP named  axi_ad6676_jesd  the output rx_data(63:0) what is the format of the data/Octets ordering with respect to I and…

  • AD6676 Front End Filter Circuit

    Hi,

    We are using AD6676 in our design and below is the signal chain.

    Can we do away with the filter section (highlighted orange) in the above chain as ADC has digital filtering mechanism inside ? (Assuming LNA is operated in linear region)

    What was the…

  • AD6676 FAQ: Why isn't the noise floor of the AD6676 flat?

    I am looking at the noise spectral density (NSD) plots shown in NOMINAL PERFORMANCE characteristics of the datasheet and noticed that they are not flat and can vary depending on the AD6676 configuration.  Why?

     

    The AD6676 includes a tunable continuous…

  • EVAL-AD6676 Stackup and Board file

    Hi,

    To understand ADC input balun routing impedance in the eval board we need stack up and board file of EVAL-AD6676.

    Please share the same.

    Thanks & Regards,

    Arunkumar P

  • RE: AD6676, problem with axi_dmac_transfer()

    Hi ,

    Our suggestion is to try to use the new version of no-OS drivers with the *.hdf file. There is a possibility that this could solve your issue. The current no-OS and hdl branches have been tested and the project runs successfully with…

  • AD6676 HDL GT REF CLK query

    Hi Sir/Madam,

    We are planning to use AD6676 IC in our design and we will be using HDL provided by Analog device for our design. Regarding that we have few queries that i have listed below.

    We are taking AD6676EBZ as reference for our design what we have…

  • Power Supply Filtering For AD6676

    Hello, Can you please Confirm the power supply filtering Design For AD6676 

  • AD6676 : Maximum Input Power (PIN_0dBFS) calculation

    Hi,

    PIN_0dBFS = 10 × log10(1/2 × RIN × (IDAC1FS)^2) is the formula mentioned.

    In the datasheet it is mentioned "the AD6676 nominal setting for IDAC1FS at 4 mA equates to a PIN_0dBFS of −3 dBm, resulting in a differential voltage swing…

  • EVAL-AD6676 SYSREF

    Inquiry Description:
    1)If EVAL-AD6676 operates with Clock synthesizer Disabled and Clock source originating from On Board Oscillator, Then from Where "sysref" is generated?
    In the Eval Board schematic, by default, it comes from an External FMC…