• AD6655: Mode 3 & 4 settings

    A customer would like to confirm the Downconverter Modes 3 and 4 specified in
    Table 18 of the AD6655 datasheet.

    For mode 3 for example (NCO and half-band filter) one can:
    Write 0x24 to Register 0x100 and
    write 0x03 to register 0x103 (not sure…

  • AD6655: For I and Q, which one is output firstly?

    A question about AD6655's decimation.I use AD6655's "Decimated IQ Mode CMOS
    Data " to output data(CLK Frequency is 100MHz, DCO frequency is 50MHz). And
    need to use FPGA to interpolate the I and Q data Rate to 100MHz. So I want…

  • RE: Request advice on data captured from AD6655-125EBZ

    this looks to be related to some coherent sampling issue. please make sure you have an integer number of cycles in your sample size. 

  • RE: Questions about the sampling rate on the AD6655 EVB

    but the actual captured data seems to be fixed at a sampling rate of about 45MHz

    how did you come to this conclusion?

  • Question of EVB-AD6655 NCO FREQ Setting

    On the Reg Map, ADDR 0x11E ~ 0x121 are NCO Frequency Value [32: 0].
    On the SPI control GUI side, NCO FREQ and Samp Freq are shown.

    1) Can Samp Freq input the input frequency value of AD6655 clk +/- (pins 49 and 50)?

    2) If a clock of 96MHz is input to the…

  • AD6655 output


    I want to know the difference between offset binary and two's complement in the output mode. How do I configure them?

  • AD6655 test pattern


    One question about the test pattern of AD6655.

    We used to test pattern of AD6655 to verify our design in FPGA.

    SPI addr = 0x0D, SPI data = 000b : Normal operation output pattern confirmed

    SPI addr = 0x0D, SPI data = 011b : -FS output pattern confi…

  • Syncing multiple AD6655


    Can someone share a scheme which shows how to sync multiple AD6655 units?

    I try to sync 4 channels of 2 AD6655 using a synced clock of 100MHz, sync signal, and configuring register 0x0ff with 1 simultaneously, Reading the user-guide from cover…

  • AD6655滤波问题