• AD6645 105MSPS Clock Input

    Hi!

    May I know if LVDS of 350mV swing is sufficient to drive the AD6645 differential clock? 

    Thank you!

  • AD6645-80 Error in ADC Codes

    Hi,

    we have designed a digitizer board with 3 ADCs. Two of them are pin compatible adcs from another vendor and one is the AD6645ASVZ-80. We have some problems with this AD data converter!

    1. Example: Sampling Frequency 40MHz, Input Sine 10k

    The…

  • 关于AD6645发烫的问题

    ADI工程师:

           您好!我最近在使用你们公司的AD6645的过程中遇到一些问题,想请教一下。我的电路图是按照AD6645的技术手册PDF画的,板子回来后进行测试,光给芯片上电,AD6645就很烫了,后来就烧了,从7、8、9这几个引脚的地方冒烟,不知道这是怎么回事。DVCC接的是3.3V,AVCC接的是5V。模拟地和数字地是分开的,通过一个0欧电阻相接。但是AD6645的裸露焊盘没有接地,不知道这会不会有影响。

  • AD6645输出二进制补码

    1.当AD6645输入为正,范围是0-1.1V时,输出的二进制补码最高位是符号位,后13位才代表实际值吗?

       那实际分辨率是13位,计算实际值时每一位代表的值 LSB= 1.1 / 2^13  这样理解对吗?

     

    2. 0V此时对应代码是00_0000_0000_00000吗?还是全为1

  • AD6645差分输入范围

    1.请问0-2V模拟信号经过AD8138转为差分信号输入AD6645,得到的差分信号是2.4±1V,是否超过了AD6645输入范围?

    2.手册上的这段话是说只能输入在2.4±0.55V吗?

  • Noise contributions when using AD6645 in undersampling application.

    I would like to calculate the noise expected when using an AD6645 in an undersampling application, to sample a signal at 180 MHz using a 55 MHz sample rate.

    Could you tell me a reference that shows me the contributions to noise and the calculations needed…

  • 关于AD8331和AD6645使用的问题

    ADI工程师:

            您好!我在使用AD6645的时候有点问题,向您请教一下。

            AD8331和AD6645交流耦合,AD8331的VCM引脚输出共模电压2.4V,AD6645的VREF引脚输出2.5V,可以把AD6645的VREF引脚直接和AD8331的VCM引脚连起来吗?

  • FPGA Reference Design for AD6644/AD6645 and AD9764 Data Converters

    To whom it may concern

    I'm searching for a reference FPGA design of ad6645 and ad9764.

    Is someone out there who has done such a design or can help me with this challange?

    Yours with kind regards

    HIDIR

  • how much dynamic range of  input signal can be measured by AD6645

    if the spurious is not counted(because the frequency of the input signal is known),how much dynamic range can be measured by AD6645.

    the frequency of input is 3MHz,sample frequency is 90MHz.

    after sample ,follow the process:

    downsample to 10MHz;

  • adc制板时,底噪控制的问题 AD6645 AD9238

    各位朋友好!

    我以前用过AD6645,现在在用ad9238画板子,做中频信号采集。板子上还有高速FPGA以及DSP。由于adc的位数比较高,14bit和12bit,我不太清楚板子的底噪要做到什么程度才能最大限度的保证adc的有效位数?当然,板子的底噪越低越好。但就算是底噪低至1mv,考虑到ADC最大输入电压可能为1V或2V,则1V/1mV=1000,也就是说只能够留下10bit左右的有效位,其他的都淹没在噪声里面了。14bitADC的量化台阶为1v/2^14=0.06mV,而板子的底噪即便是1mv…