• ad5761R

    I just got the AD5761R, to do a better accuracy of the DAC output module, the simpler the better. Voltage range between 0-3.3V can be, and can control the output of RAMP and SIN waveforms, is there any reference design and development routines?

  • AD5761R


  • AD5761R


  • AD5761R




  • AD5761R OUTPUT

    I am using the AD5761R chip, why does the software fully reset when there will be a signal output on the SDO? Then VOUT, there is no voltage output. The following image is a schematic of the chip design, where VCC1 is 3.3v.

    Here's my time series chart…

  • AD5761R驱动


  • [AD5761R/AD5721R]Eval Schematic


    I would like to make clear about EVAL schematic of AD5761R/AD5721R.

    According to UG-751


    Page 7, pin#9 is connected to GND with CAP.

    But Datasheet…

  • AD5761R shorting the DGND and AGND


    I want to maintain single ground on the board for the chip AD5761R.

    So is it OK to have common ground connection, i.e. short the DGND and AGND together?

    Kindly let us know.

    Thanks & Regards,

    Nanjunda M

  • AD5761R output is not right.

    I am using an AD5761R DAC connected to an FPGA. All signalling and signal timing to the DAC looks good and I am doing a simple test:

    Signal Conditions for this test: RST, CLR and LDAC are held high in the FPGA.
    SYNC, CLK and Data come from the FPGA.


  • RE: AD5761R EXPOSEDPAD connection

    Hi ,

    Please connect the EPAD to the Vss pin(Pin 4) or you can leave it floating.