• ad5761R

    I just got the AD5761R, to do a better accuracy of the DAC output module, the simpler the better. Voltage range between 0-3.3V can be, and can control the output of RAMP and SIN waveforms, is there any reference design and development routines?

  • AD5761R

    我刚拿到AD5761R,要做一个精度提高越好的DAC输出模块,越简单越好。电压范围在0-3.3V之间就可以,并且输出RAMP和SIN波形,有没有什么参考的设计方案和开发例程?

  • AD5761R

    我刚拿到AD5761R,要做一个精度提高越好的DAC输出模块,越简单越好。电压范围在0-3.3V之间就可以,并且可以控制的输出RAMP和SIN波形,有没有什么参考的设计方案和开发例程?

  • AD5761R

         我正在使用AD5761R这个芯片,为什么软件完全复位的时候也会有SDO上的信号输出?然后VOUT,没有电压输出。下图是芯片设计的原理图,其中VCC1为3.3v。

    时序图如下,是因为发送的数据有问题吗?

    有大佬速度解惑一下。

  • AD5761R OUTPUT

    I am using the AD5761R chip, why does the software fully reset when there will be a signal output on the SDO? Then VOUT, there is no voltage output. The following image is a schematic of the chip design, where VCC1 is 3.3v.

    Here's my time series chart…

  • AD5761R驱动

    VerilogHDL语言写AD5761R驱动,有参考案例吗?

  • [AD5761R/AD5721R]Eval Schematic

    Hello, 

    I would like to make clear about EVAL schematic of AD5761R/AD5721R.

    According to UG-751

    http://www.analog.com/media/en/technical-documentation/user-guides/EVAL-AD5761RSDZ_UG-751.pdf 

    Page 7, pin#9 is connected to GND with CAP.

    But Datasheet…

  • AD5761R shorting the DGND and AGND

    Hi,

    I want to maintain single ground on the board for the chip AD5761R.

    So is it OK to have common ground connection, i.e. short the DGND and AGND together?

    Kindly let us know.

    Thanks & Regards,

    Nanjunda M

  • AD5761R output is not right.

    I am using an AD5761R DAC connected to an FPGA. All signalling and signal timing to the DAC looks good and I am doing a simple test:

    Signal Conditions for this test: RST, CLR and LDAC are held high in the FPGA.
    SYNC, CLK and Data come from the FPGA.

    Clock…

  • RE: AD5761R EXPOSEDPAD connection

    Hi ,

    Please connect the EPAD to the Vss pin(Pin 4) or you can leave it floating.

    Cheers,

    Ivan