Would like to confirm that AD5676 reset pin is edge sensitive. I understand the datasheet documents it. Was hoping to use card power on reset to reset AD5676.
Now i use the AD5676 as compensation. i check the timing characteristics in the datasheet and use FPGA realize it. But the VOUT value cant be updated by changing the SDI's data.
Below is the scheme and timing scope. (SCLK = 9.6MHz, the timing operation…
I have a question about software reset for AD5676.I sent "software reset"(0x6000) to AD5676, but the AD5676 did not move to reset condition.
Please see the attached file.These waveforms are SPI communication between PC and AD5676.
AD5676 does not work..
Three AD5676 are attached. Operate with DCEN.
The contents of 24-bit data are as follows.
Command：Set up the DCEN register (daisy-chain enable)
Address Bits:Selected Output DAC channel～
DATA BITS：[0000 0000 0000…
We are already using the readback command successfully as per the data sheet instructions for a single operation.
Send "1001" + (4 bit register address) + "0000000000000000" - read back command of specified register
I have a couple of questions concerning the above device.
1. We would like to drive the SCLK continuously in our application.
Can you please confirm that the SYNC input internally gates the SCLK in the device?
This is implied by the description but…
Please advise me the gain error drift of the AD5676.
Question: Figure 46 on Rev B. of Datasheet of AD5672R/AD5676R. What is the test condition for this figure? One DAC change at a time and they are all compiled later? Is this just one DAC changed once or multiple times?
What is the difference between AD5676 and AD5676R?