Hi
How I set the register to clamp output current ? Such as set the output current 25mA output, How i set the clamp current to 30mA or 20mA ?thanks
Hi
How I set the register to clamp output current ? Such as set the output current 25mA output, How i set the clamp current to 30mA or 20mA ?thanks
Hi
I am working on AD5560 and I can not make AD5560 output voltage correctly.
My configurations are as follow:
AVDD = +28V, AVSS = -5V VREF = +5V
OFFSET_DAC code = 0x0 Force DAC(x1) = 0xFFFF
Force DAC's OFFSET AND GAIN REGISTERS c…
你好:
AD5560使用的时候,AVDD供电+28V,AVSS供电-5V,电流范围选择2.5mA。
设置offset DAC的值为0,输出DAC的校准寄存器中,c寄存器为0x8000,m寄存器为0xFFFF,x1设置为0xFFFF,此时输出为14.1V左右。
按照datasheet上提供的公式,计算Vout应该为+25.62V。
关闭钳位功能(clen pin下拉,同时配置reg2中的CLEN bit为0),输出仍然没有变化。
请问还有什么设置会影响Vout的输出…
Hello,
I have some quetions about current clamps AD5560.
1) If i do not use offset (CLH, CLL), it is mean that current range is simmetrical (for example -500 mA to 500 mA)
2) I use current range -25...25 mA, then i set CLH 18,75 mA - measuring value is…
I am trying to observe the output slew rate characteristic of AD5560 according to the load capacitance,
but a simulation model cannot be obtained. Please provide a corresponding simulation model.
Dear Sir/Madam,
I would like to check the kIck/Drop response of AD5560 datasheet.
Do I check with SPICE? Or can I check with LTspice?
I can't check my library in LTspice.
ex. Datasheet Figure 35
stic
Dear Sir or Madam
If only the DVCC of AD5560 be supplied by 3.3V , refer to DGND . Can I access the all the registers ?
For there is a phenomenon , sometimes , if I disable the negative power rail which supplies AVss , HCAVss of AD5560 . The registers…
1、关于AD5560的FIN DAC(Vref=5V)为什么不是391uV而是381uV?
1LSB=5V/65535 *5.125=391uV
2、DS.中有一句计算方法“The fastest ramp rate is 0.775 V/μs (for a 5 V reference and an 833 kHz clock using a 2032 LSB step size and divider = 1).”
我的理解ramp rate=2032LSBs*RCLK…