In the data sheet for AD5545/AD5555 (rev. I), in the figure 22, there is a voltage regulator ADR03 connected by VIN to VREF of AD5545/AD5555. Is it an error? Or, maybe, there is some sense in this connection?
And, BTW, another question about this scheme…
Most of the AD55xx Iout DACs are not suitable to be used with IOUT2 (AGND) biased above ground.
For AD5555, the highest voltage that you can raise on the AGND pin 0.5V provided VDD is 5V and is very stable.
| AD693 |
| AD5410 |
| AD5412 |
| AD5420 |
| AD5422 |
| AD5735 |
| AD5755 |
| AD5755-1 |
| AD5737 |
| AD5757 |
| AD5421 |
| AD421 |
| AD5758 |
| AD7569 |
| AD7669 |
| AD7868 |
| AD7869 |
| AD5593R |
| AD5592R |
| AD5940 |
| AD5941 |
| AD7293 |
| AD7294-2 |
| AD7292 |
| AD5590 |
| AD7294 |
| L… |
DAC模拟输出考虑因素
DAC的模拟输出可能是电压或电流。两者情况下，可能都需要知道输出阻抗。如果对电压 输出进行了缓冲，则输出阻抗将很低。而电流输出和未缓冲的电压输出将存在较高阻抗， 并还可能具有电抗性分量以及纯粹的电阻性分量。在有些DAC架构的输出结构中，输出阻 抗与DAC上的数字码字成函数关系，这点应会在数据手册中明确注明。
理论上，电流输出应当连接到电阻为零欧姆的地电位。在实际应用中，该输出将采用非零 阻抗和电压。“顺从性”标题下只是定义了该输出可耐受的电压偏差大小，端接电流输出 DAC时应当注意到此项技术规格…
If you are using or plan to use the AD5415 12-bit DAC chip in a daisy-chain configuration, you need to read page 20 of the marked up data sheet attached. If you are using the SDO output of even a single AD5415, then you also need to see the erratum marked…
