大家好！

       本人正在使用16bit，32通道的DAC芯片AD5372进行相关开发，使用pic18f4431进行控制。SDI、SCLK、nSYNC、nLDAC等信号均和datasheet中的时序图一致，但是nBUSY信号始终未能出现时序图中指示的负脉冲，因此D/A转换始终未能实现。综上，本人有如下疑问：

       1、nBUSY信号的定义中解释为Digital Input/Open-Drain Output，请问该信号作为输入或者输出是否需要进行配置，如果需要配置应该在何处进行。

       2、该芯片若干寄存器的default值均能满足我的使用要求…

I have an circuit that uses the AD5372 DAC with VDD = +15V, VSS = -15V, and DVCC = +3.3V.  Are there any sequencing requirements for these rails?

Thanks,

Matt

I am designing a product with an AD5372 DAC. I am having a couple of problems. I would

really appreciate if an expert from Analog could help me out with this.

1) the DAC outputs are not monotonous and seem to make no sense compared to the

formulas…

The datasheet says the exposed paddle should be connected to Vss. Other datasheets say ground. Which is correct?

What is the 24 bit serial data string assignment for the AD5372 Control Register?

I must toggle the A/B Global Select Bit to be able to select X2A or X2B.

Not much information on the data sheet re.the Control (3 bits), OFS0 (14 bits), OFS1 (14 bits) or…

Hi,

I have been googling for a while to try to find the best way to use the AD5372 with a linux board.

I want that the DAC outputs 32 channels of "audio" signal but limited to a 1kHz sample rate. So it looks like it is possible and that an Alsa driver…

I designed low noise 32-channel DAC modules for ion-trap applications.

And we observe that on some of the boards the DAC consumes much higher current on negative rail than specified.

I measure 60mA, this current heats the chip significantly and gets…

Hello,

Do you have app note for this device to use up to 32 channels on the layout caution?

Thanks.

If the Sync line is held high on the AD5372, but SCLK and SDI  are still changing will there be any ramifications on the DAC outputs?