Hi,
I am using AD5362 in my design which is interfaced with sitara processor.I modified kernel and added device tree node. Device is getting enumerated in /sys/bus/iio/devices.
The Vout of the DAC is fixed at 0.114V and not changing at all and I am not…
Hi,
AD5362 is implemented in a driver for AD536x family.
You can try to instantiate it just as a simple SPI device under correct SPI bus at the required SPI chip select.
It should be something like this:
dac@0 {
#address-cells = <1>;
#size-cells …Hello,
SDO timing spec is not clear. Looking at Figure 5. SPI Read Timing in datasheet Rev.A, set up/hold time associated with SCLK rising or falling edge is not clear. Actually the diagram does not pointed any timing line on SDO. Please clarify timing…
Hello,
I have a question regarding the RESET function on the AD5362. According to the datasheet:
The reset function is initiated by the RESET pin. On the rising edge of RESET, the AD5362/AD5363 state machine initiates a reset sequence to reset the X…
Q.
How do I select a reference for the AD536x and AD537x DACs?
-----------------------------------------------------------------------------------
A.
A reference value from +2V to +5V can be used with the AD536x and AD537x. Using the default register…
Q.
How Does the PEC Function Work in AD536x DACs?
--------------------------------------------------------------------
A.
The AD536x parts have a Packet Error Check function (PEC) which indicates to the user that the serial write was accepted as valid…
Q.
How do I use the offset register in AD536x and AD537x DACs?
------------------------------------------------------------------------------
A.
The Offset register sets the offset voltage of a 14-bit DAC. The DAC can be used to move the output span of…
Q.
How do I select an output range for the AD536x and AD537x DACs?
----------------------------------------------------------------
A.
The output span of the AD536x and AD537x is principally determined by the reference voltage on the VREFx pins. The m…
