Q1. If the reference input of AD5312 become 0V during the buffered mode, what AD5312 happen ?
Q2. The customer hopes the reference voltage performs ON/OFF control of Vout regardless of buffered or unbuffered. Is it possible ?
Please confirm that if the LDAC pin is held low, then the data is clocked straight through from the input register to the DAC register. Please clarify at what instant does the DAC change its output value (after the 16th bit is clocked in? after the SYNC…
D6B 根据ADI的编号就是 AD5312 一个DAC.
Any additional help would be greatly appreciated. With more experimentation we can individually kill the 3 volt supply to the DAC and the DAC will stay locked up. Its not until we kill the 3 volt supply and the control signals( LDAC, SYNC, DIN, SCLK …
I was wondering if something could be done with the LDAC pin because on all the application shown at the end of the datasheet, LDAC is often not represented. I want to keep LDAC low but Im not sure if this can be done. Could you please confirm?
What should be happen in input shift register when SYNCb is deasserted before 16th falling edge of SCLK?
My expectation is that the content of the input shift register should be cleared and the content of the input register should not be changed…
I'm facing a weird problem with a sport on ADSP-21161.
The sport is used to drive a AD5312 DAC: I configure it for data transmit, internally generated clk and fs, late frame sync, active low.
I've always used it in data dependent mode…
single-supply Operation：2.7V to 5.5V，根据自己所需要的电路供电电压和输出电压…