My customer is considering AD5310R.
The AD5310R data sheet says “If SYNC is high after 16 falling clock edges occur, it is interpreted as a valid write and the first 16 bits are loaded to the input shift register.”However, SPI Command Operation…
Please refer to following URL.
AD5310R | datasheet and product info 10-Bit nanoDAC, SPI Interface and 2 ppm/°C On-Chip Reference | Analog Devices
I think that you confirmed not R product.
Q1. What is new?
A1. The nanoDAC+(TM) family offers improved analog performance in terms of INL and glitch energy specifications.. Some members of the family, those with a part number ending in 'R', for example AD5686R, include a low drift…