• RE: Time chart about AD5302 DAC

    I just discussed about this with our customer.

    He will also check this motion by one sample AD5302.

    This is very important and need the answer soon.

    So can anyone answer this?

    Thanks Kaos

  • The ADL5802 evaluation board has a 180 degree phase difference between IF1P and IF2P.Is this intentional?

    I am using the ADL5802 to down convert two signals for phase comparison using the AD5302.

    It appears the IF signals are 180 degrees apart when two in phase signals are put in.

    Is this expected?

  • AD5302输出直流电压

    请教ADI工程师,我用8位的AD5302输出一个基准电压信号给程控放大器,控制其增益;现在调试,发现,DA在0V输出和5V输出信号时直流电压信号;其他的电压信号,就是带偏置的类似正弦波信号;均值电压就是我设定的电压值; 芯片供电电压时+5V;REFA与REFB都是用REF195给的+5V参考电压。附件是原理图和测试的电压波形图!麻烦帮我分析下?非常感谢!

    原图如下:

    波形图:A,B通道输出2.5V的波形

    A通道

    B通道

  • [征文] IN118的基准源用AD的芯片,上面写着D6B,困饶我很久了 AD5312


    这个芯片(AD9833)的名字我猜的,可忽略看,如果是这个芯片,左看右看也不知是干吗呢?

  • AD5312 Lock up

    We are using an AD5312 that works flawlessly.  It outputs the analog values we are looking for and all of the control signals look good.   The problem we are experiencing is that occasionally during electrical noise it locks up and begin to Output 3 volts…

  • [AD5322] Deasserting SYNCb before 16th clock edge

    Hi,

    What should be happen in input shift register when SYNCb is deasserted before 16th falling edge of SCLK?

    My expectation is that the content of the input shift register should be cleared and the content of the input register should not be changed…

  • AD5312 and LDAC

    Please confirm that if the LDAC pin is held low, then the data is clocked straight through from the input register to the DAC register. Please clarify at what instant does the DAC change its output value (after the 16th bit is clocked in? after the SYNC…

  • AD5232 Daisy Cain Mode Issues

    I am using 7 x AD5232 in Daisy Chain mode. The timing is not in the correct
    order. Are there any known problems in this configuration?

     

    There are no known issues with the AD5232 in daisy chain mode. The SDO line and
    SCLK lines are gated…
  • ADI芯片辨识、型号查找

    看看截图: