FAQ
My SPI CPOL=0,CPHA=0.I use Rwa(D)=(256 - D)/256 x Rab +Rw calculate value of resistance.
Theoretically when I set 0xff voltage at WA terminal is lowest,set 0x00 voltage at WA terminal is highest.but I set 0xB0 voltage at WA terminal higher than set 0x7F…
对于AD5160,采用5V供电,其A、B、W端能否接受负电压,如-0.5V(有大电阻限流)?
我看datasheet,有小字备注:电阻端A、电阻端B和电阻端W彼此没有极性限制。
设计图如下所示。
请大神们抽空解答一下,谢谢!
Hello,
I have a question about typical oscillator circuit and AD5160.
In typical oscillator circuit, if we want to avoid clock signal reflection or overshoot when clock at rising edge, there is recommend to add a resistance to reduce them,
however, in…
I just bought EVAL-AD5160DBZ evaluation board and EVAL-MB-LV-SDZ motherboard to control potentiometer AD5160 using PC. But when I installed the software provided by your company, something is wrong with software. Please find the detail in the attachment…
Hi,
An extra question strongly related to this: I need to have this working in SPI mode 3, as I have other devices on the bus, which only works with an inactive high CLK.
When I look at the datasheet for AD5200, which is somewhat worded similarly…
i am using altium and cant get ultra librarian working. all im after is a drawing for the PCB footprint of the SOT23-8 device
thanks
carl
Hi
Is there limitation about CLK signal for AD5160?
It could not the right setting by slow slew rate clock signal.
It is OK when SDI is 0xFF or 0x00, but in other setting,it is unstable.
In our test, clock signal spent 10usec to rising or falling…