• AD5160 Set 0x00 to 0xFF,The voltage I get is not linear.

    My SPI CPOL=0,CPHA=0.I use Rwa(D)=(256 - D)/256 x Rab +Rw calculate value of resistance.

    Theoretically when I set 0xff voltage at WA terminal is lowest,set 0x00 voltage at WA terminal is highest.but I set 0xB0 voltage at WA terminal  higher than set 0x7F…

  • The maximum acceptable clock rise time for the AD5160's reliable operation?

    What is the maximum acceptable clock rise time for reliable operation of the


    When using the SPI Interface, it is assumed that the master has strong drivers
    so that the input buffers don't have hysteresis. To summarize, we cannot

  • 数字电位器AD5160的A、B、W端能否接受负电压





  • AD5160 as resistance to eliminate clock reflection


    I have a question about typical oscillator circuit and AD5160.

    In typical oscillator circuit, if we want to avoid clock signal reflection or overshoot when clock at rising edge, there is recommend to add a resistance to reduce them,

    however, in…


    I just bought  EVAL-AD5160DBZ evaluation board and EVAL-MB-LV-SDZ motherboard to control potentiometer AD5160 using PC. But when I installed the software provided by your company, something is wrong with software. Please find the detail in the attachment…

  • RE: AD5160 SPI parameters?


    An extra question strongly related to this: I need to have this working in SPI mode 3, as I have other devices on the bus, which only works with an inactive high CLK.
    When I look at the datasheet for AD5200, which is somewhat worded similarly…

  • RE: IBIS model for AD5160 and AD5641

    This question has been assumed as answered either offline via email or with a multi-part answer. This question has now been closed out. If you have an inquiry related to this topic please post a new question in the applicable product forum.

    Thank you,
  • AD5160 SOT 23 8 pin footprint drawing required

    i am using altium and cant get ultra librarian working. all im after is a drawing for the PCB footprint of the SOT23-8 device



  • AD5160 slow CLK signal


    Is there limitation about CLK signal for AD5160?

    It could not the right setting by slow slew rate clock signal.

    It is OK when SDI is 0xFF or 0x00, but in other setting,it is unstable.

    In our test, clock signal spent 10usec to rising or falling…