• AD4000 series Status register

    I am connecting with an AD4003 using an FPGA and have already successfully gathered data using the 3-wire mode. However, I do not seem to be able to read back the status register (and perhaps I might not be writing correctly either). I have re-read the…

  • Example c-code to read ADC data from AD4000

    Hello,

    Is there any pseudo c-code available to read the adc data from the AD4000 over SPI?

    AD4000 is connected to a PIC32 in our design.

    Thanks,

    -Mohi

  • Feasibility of using multiple AD4000 with the Linux Driver / IIO framework to record all channels simultaneously to file?

    I'm trying to determine the feasibility of using multiple AD4000 with the provided linux drivers and the IIO framework to record all channels simultaneously to file (like an 4x channel o-scope).

    This design uses a zynq 7000 series FPGA using linux…

  • AD4000 reference voltage and power consumption

    Hello,

    A couple of questions about AD4000 design:

    It is a 1.8V device; however, the current consumption is not mentioned anywhere in the DS (or I am not looking hard enough). On page 6 of datasheet, power dissipation numbers are given for different sampling…

  • RE: AD4000 Serial Interface Issue

    Hello,

    Thank you for the detailed scope shots.

    It's not exactly clear why the SDO is going high-Z before 16 SCK periods, but I suspect it may have to do with the fact that there is an additional CNV rising edge that is not required that the AD4000 doesn…

  • Hello I’m using your software When I use an ADC\AD4000 example circuit 1st I provide different types of signals sinewave, exp, rectangular Vin voltage contains some errors due to resistance so this ADC gives incorrect OUTPUT How can I solve this problem...

    Hello

    I’m using your software

    When I use an ADC\AD4000 example circuit 1st I provide different types of signals sinewave, exp, rectangular  Vin voltage contains some errors due to resistance so this ADC gives incorrect OUTPUT

    How can I solve this…

  • AD4000 SPI Timing

    Hello, I am trying to implement a SPI driver for the AD4000 on the UG-1042 eval board. The goal is to use 4 wire mode since we will need to enable high-z mode.  We are first trying to enable a conversion. It seems like bit is shifted out of the ADC as soon…

  • AD4000 ADC.

    We are trying to set the command register for writing operation and set the ADC to 2MSPS Turbo Mode. But we are unable to read the register status as SDI and SDO have different polarities. We are trying to send the command as described is page 26 of AD4000…

  • AD4000系列的ADC采样CONV必须要一个上升沿吗?

    从ADI AD4000系列的手册中看到,启动CONV需要一个上升沿,这里能将conv接标准的SPI的CS脚吗?标准的SPI的CS脚不会产生上升沿。

  • top module HDL(FPGA) design for AD4000

    Hello support team,

    Now I'm designing Xilinx program as host for AD4000. That is, I'm trying to design for evaluation of EVAL-AD40XX-FMCZ with AC701. Now, I already have gotten the HDL design which is provided by ADI on the AD4000 product web page. There…