I have a idea to test project, I use sru adc->dai_pin01 and dai_pin01-> dai_pin02 dai_pin02->dac.
the codec ad1939 is standalone mode, use i2s 48k, dsp pcg give the BCLK and LRCLK to codec ad1939.
and I can hear the sound. but…
For the AD1939 CODEC, data sheet specifies sample rates of 128/176.4/192 kHz if you set control register to '10'. We did that and are at 192 kHz. How do we get 128 kHz instead ? That's the ADC/DAC sample rate we really want. Thanks.
I'm working with the ADSP-21489 EZ-board, which has an AD1939 clocked on a 12.288 MHz oscillator. My test input is an SPDIF audio stream @ 48kHz. Ultimately I want to work in some proprietary routines that require the sample rate to increase to 4x (i…
For the DAC Data Bus it looks like there are a couple of choices:
2. Daisy Chain the AD1939
Option 1 seems simpler with a lower bit clock frequency. Would either work and do you have a…
If I configure the DAI pins in I2S (no package),and how many input and outpute channels can support?
And another question,the signal to noise ratio of AD1939 can't satisfy our project, May I have other chips which have same pins with AD1939.
We do not have a driver in a form that will help you. However, you can run out the AD1939 register definitions from SigmaStudio and use this as a reference for having your PIC send out SPI commands to configure the AD1939.
The best way to go about understanding the filter is by simulating it. Attached is a schematic that you can run simulations and play around with.
This DAC output filter can be used with the AD1939 (Figure 31 of the AD1939 data sheet).
I am using the AD1939 codec in the 21469 EzKit. I see the clock (12.88Mhz) for this Codec is generated internally by a crystal. I would like this frequency to be generated by a TIMER in the AD21469. How could i map this timer as the CLK to…