1. PLL mode; master clock input from MCLKI = 12.288M (256×fs, here fs=48k); 12.288M --> PLL --> the internal master clock = 24.576M. The internal clock for the DACs varies by mode: 512×fs(48kHz mode), 256×fs(96kHz mode), or 128×fs(192kHz…
Keep in mind that the AD1934 is the single-ended version of the AD1933.
Hello Dave,Thank you. I have so many questions.1. AD1933 datasheet says: AD1933 provides 8 DACs using patented multibit sigmadelta (Σ-Δ) architecture. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation, operating…
I am waiting for your reply of "AD1933,Dual-Line,TDM Mode".
1，relation of MCLK BCLK LRCLK
after reset, BCLK s is 64 per frame, so BCLK = MCLK/4 = 3.072Mhz，LRCLK = BCLK / 64 = 48K 。
Is it correct？
2，default Word Length is 24bit，but LRCLK = BCLK…
Hello, I want to use AD1933 as slave, it connect with ADSP21489. In ADSP21489, I use PCGA generate CLK(3.072M) and frame sync clock(48k) to AD1933. And I send a sinusoidal signal, but the AD1933 output pin have not ideal output, it is discontinuous, look…
I drive a AD1933 in slave mode. The digital input of DAC is connected directly to FPGA. The AD1933 runs in TDM - Mode.
The AD1933 becomes MCLK (Master Clock: 12,288MHz), BCLK (Bit Clock: 12,288MHz) and DACLRCLK (DAC LEFT RIGHT Clock: 48 kHz) from…
No, you cannot use the TDM modes in Standalone mode. Have a look at the application note I wrote a few years ago detailing how to use a small low-cost micro-controller to boot up the codec in TDM mode. It includes the code in the App…
First thing I would suggest is to substitute an ADAU1966 instead of the (2) AD1933. Otherwise, do you have some kind of key to define the letters that are in the circles?