• AD1933

    1. PLL mode;
        master clock input from MCLKI = 12.288M (256×fs, here fs=48k);
       12.288M --> PLL --> the internal master clock = 24.576M.
       The internal clock for the DACs varies by mode: 512×fs(48kHz
       mode), 256×fs(96kHz mode), or 128×fs(192kHz…

  • AD1933 & ADAU1372

    Hello Dave,
    Thank you. I have so many questions.
    1. AD1933 datasheet says: AD1933 provides 8 DACs using patented multibit sigmadelta (Σ-Δ) architecture. The DACs include on-board digital reconstruction filters with 70 dB stop-band attenuation, operating…

  • AD1933 SPI Communications

    Hi Everyone,


    I have been struggling with an issue now for some time and I have not been able to figure out what I need to do to get this to work properly.


    I am using the AD1933 along with an Atmel 32bit microcontroller (3.3V I/O). I send data to…

  • AD1933 Clock Settings, SPI Read/write


    I am setting up this DAC and I am not clear after reading the datasheet what clock settings to use.

    • PLL on-board, which can take input reference frequency from different sources.  This generates an internal clock at 256, 512, fs
      • If I am using t…
  • AD1933 standalone mode

    On page 12 of the datasheet it specifies that in standalone mode the ad1933 only work in I2S format. Is there a workaround for TDM or does this require a microcontroller to get TDM format working? If it needs a microcontroller are there recommended models…

  • AD1933 daisy chain SPI


    I would like to connect to three AD1933 DACs from a host, but the host only has one SPI chip-select. Could I use SPI daisy chain method to connect to AD1933 DACs?

  • AD1933 8-Channel DAC


    I'm working with ADSP-SC584 Sharc DSP.

    Is there any BSP support for AD1933 8-Channel DAC?

    This DAC is not part of EZ KIT.


  • question about 21489 connect ad1933

    Hello, I want to use AD1933 as slave, it connect with ADSP21489.  In ADSP21489, I use PCGA generate CLK(3.072M) and frame sync clock(48k) to AD1933. And I send a sinusoidal signal, but the AD1933 output pin have not ideal output, it is discontinuous, look…

  • AD1933 DAC generate undesired signal


    I drive a AD1933 in slave mode. The digital input of DAC is connected directly to FPGA. The AD1933 runs in TDM - Mode.

    The AD1933 becomes MCLK (Master Clock: 12,288MHz), BCLK (Bit Clock: 12,288MHz) and DACLRCLK (DAC LEFT RIGHT Clock: 48 kHz) from…

  • AD1933 default standlone timing operation



    1,relation of MCLK BCLK  LRCLK

         after reset, BCLK s is 64 per frame, so BCLK = MCLK/4 = 3.072Mhz,LRCLK = BCLK / 64 = 48K 。

         Is it correct?

    2,default Word Length is 24bit,but LRCLK = BCLK…