• AD8213 output error is too large,How to deal with the problem of chip consistency?

    1 .SCH

    2 . Test method:

    (1) It is powered by 24 V battery, ,and the load is 30 ohm resistance.

    (2) The PWM port of circuit board is output by 35% and 70% duty cycle controller, and the Rshut is 0.05 ohm, ± 0.5%。

    (3) The differential input voltage…

  • RE: Problems running examples in matlab by adrv9009

    Hello, there I solved it by changing the profile. Place the Tx_BW200_IR245p76_Rx_BW100_OR122p88_ORx_BW200_OR245p76_DC245p76.txt and followed suit. I wonder why I couldn't use the other profile that changes some parameters like the frequency of the device…

  • AD9361 RX frequency or clock mismatch

    Hello,

    I have setup and successfully initialized an FMCOMMS-3 AD9361 radio with the no-OS library on a bare-metal Xilinx platform. I'm using a HackRF with GNU Radio to transmit a persistent sinusoid of arbitrary frequency via SMA cable directly into the…

  • RE: AD9371 PLL set up error

    I tried using a standard profile as well with the same results

    <profile AD9371 version=0 name=Rx 82, IQrate 100.000>
    <clocks>
    <deviceClock_kHz=100000>
    <clkPllVcoFreq_kHz=12000000>
    <clkPllVcoDiv=3>
    <clkPllHsDiv=4>
    <…

  • AD9364 RX FIR Decimation Data Rate vs. DATA_CLK rate

    I'm using DUAL PORT FULL DUPLEX MODE (CMOS) from page 95 of UG673.

    I'm using the filter wizard to configure AD9364 TX and RX to operate at 5 MHz baseband datarate. I get this for RX

    AD9361_RXFIRConfig rx_fir_config = {

    3, // rx

    -6, // rx_gain

  • JESD204 link failures with DAQ2 on custom Arria 10 board

    I'm working on a custom Arria 10 SOC board with the DAQ2.  I started with the a10soc project as my reference and made required modifications for our board.  HDL design is compiling and FPGA configures.  During boot to linux, I'm getting JESD204 link…

  • IRMS OFFSET Calibration on ADE7753

    Hi Guys, I´m working to finish my project with ADE7753, and I have a little problem to take out the residual current increased by Rogowski current sensor and circuit driver to measure current in CH1. I have observed it on IRMS Register 

    My device have…

  • RX/TX cp cal problems when re-congfiguring 9364 without resetting AD9364

    Because we want to configure AD9364 many times in one proram for testing the single configuration time.

    When ini-configuring,after RX/CP cal done,244[7]/284[7] would be set.

    But in the second congfiguration,when starting RX/TX cp cal, check 244[7]/284…

  • AD9174-FMC-EBZ Poor Spurious Performance

    Hi everyone,

    I am evaluating AD9174  DAC Performance using AD9174-FMC-EBZ  with below mentioned configuration.

    I am using in NCO Only Mode (without JESD204B link)

    Select Chip to Configure: AD917x Only

    AD917x Clock Source : Direct Clock (PLL OFF)

    DC Test…