• AD9361 TXFIR int 0 RXFIR dec 0 mode Highest OSR


    These are the inputs given by us for configuring AD9361.

    {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},// rx_path_clock_frequencies[6] *** adi,rx-path-clock-frequencies 

    {1024000000, 64000000, 32000000, 16000000, 8000000, 4000000},/…

  • Building CCES system SEC service support libraries for ADSP-SC573

    According to "Allow SHARC SEC Code to Skip the SEC Reset" in the Linux Add-in for CrossCore Embedded Studio (CCES) User's Guide section 6.7.3 "Coordinate the SEC Initialization for multicore Development" on page 243, in order to have SHARC…

  • AD9361 Tx/Rx RF PLL unlock problem in TDD Mode

    When operating the AD9361 in TDD mode, the Rx RF PLL and Tx RF PLL sometimes become unlocked.

    The problem occurred on the RF SOM (Rev E) mounted on the ADI FMC carrier board using the latest AD9361 HDL reference design available from the GIT repo and…

  • simple or basic CW and Broadband noise flowgraphs examples


    Where can I find some simple or basic CW and Broadband noise flowgraphs examples in Gnuradio? Any links or samples would be highly appreciated.


  • adv7181D decode VGA (640 x 480 @60Hz) to 8 bit YUV 422

    PCBWe are currently using an ADV7181D to decode VGA (640 x 480 @60Hz) to 8 bit YUV 422.But there is no register

    configuration in the script you provided.So I want to ask you something:

    1、Does it support doing that  to decode VGA (640 x 480 @60Hz) to 8 bit YUV 422…

  • adv7842 input have signal adv7511 output is invalid

    our 7842 hdmi register configure is :


  • ADAS1000 clock problem

    Hi, I'm using ADAS1000. Unfortunately when did place board component, I placed crystal wrong and cause short circuit between XTAL1 & XTAL2 pins.

    Now I'm trying to connect ADAS and get data from it. I get frames but only have headers and crc value…

  • Strange Data Glitch on AD4003 FMC on ZC706


    We noticed a strange data glitch on the AD4003 running the evaluation FMC card - shown below. Captured conditions were CNV rate of 1.6 MSPS and SCK rate of 80 MHz using VIO = 2.5V.  We've changed the timing of our signals (CNV, SCK) and tried VIO…

  • AD9361 initialisation sequence


    I am developing a SDR via SIMULINK, starting wiit the Tx. 

    The simulink models are fine, generate code and also work via the AD963x block to give an OFDM signal. I can download the HDL and verify that I see digital output on a Logic Analyser

    I now need…

  • Unable to measure the correct reflected power using ADL5920 EVAL board


    I have just purchased and setup my ADL5920 EVAL board and trying to measure the S11 of some simple loads such as 50 ohm matched load and T-resonator etc.

    I am able to setup the board and connect it with quikeval.

    I am also able to calibrate the board…