Spi mode of AD7770

In the page 39 of AD7770 datasheet, there is an illustration that shows that the -CS, SDO, SDI and SCLK are to be connected to the FPGA or DSP.   My question,  is the SPI in AD7770 act as a slave when connected to the FPGA or DSP?

It means the SPI in the FPGA is acting as a master and the AD7770 is the slave.   I am asking this because I am confused.

The label below the arrow line going to FPGA or DSP says "SPI MASTER INTERFACE".  

When I check pin function description, Pin 19 is an input pin,  describe as

" DCLK Frequency Selection Pin 2 in Pin Control Mode (DCLK2). See Table 15 for more details.

  SPI Clock in SPI Control Mode (SCLK)."  

Based on my understanding on the SPI, the master generates the clock signal and the slave takes the clock signal for the operation.  

  • 0
    •  Analog Employees 
    on Sep 7, 2016 12:31 PM


    the AD7770 has two interfaces, the SPI and the DOUT.

    For clarifications, the DOUT acts as a master SPI.

    The SPI interface pins are /CS, SCLK, SDI (MOSI) and SDO (MISO)

    the DOUT pins are DCLK (SCLK), /DRDY (/CS), DOUTx (MOSI)

    Let me know if you have any more questions,



  • 0
    •  Analog Employees 
    on Sep 8, 2016 8:17 AM

    Hi Darwin,

    /DRDY acts as a /CS in the DOUT interface (master SPI).

    You can read SD data conversions thru the slave SPI, in this case, you must monitor the DRDY pin to check when the data is ready for reading back.



  • Hello,

    I would like to to confirm my understanding

    1.  DOUT will transfer data in SPI protocol, acting as master, with DOUT0

    as the MOSI.  DRDY serves as the CS.  As shown in the Figure 113.

    2.  SPI control, the SPI is slave and DRDY will still output a pulse at

    every end of conversion.



    On Wed, Sep 7, 2016 at 8:32 PM, musach <

  • 0
    •  Analog Employees 
    on Sep 13, 2016 10:18 AM

    Hi Darwin,

    As previously mentions, SPI is an slave interface, DOUT acts as a master SPI.

    The DOUT interface can operate a single SPI, dual SPI or quad SPI depending teh number of DOUT lines enable.

    256 samples per line cycle @ 60Hz, equates to 15360 samples per second, so program the SRC registers appropriately.



  • Hello Miguel,

    I have additional question. This is related to Table 13.

    When the combination of:

    CONVST_SAR State  = 1, Format1 = 1,   Format0 = 0,  the Data Output mode is

    SPI output.

    With regards to this input combination, which pin are we going to connect

    to for the SPI output?

    Is the SPI of the device AD7770 a slave spi or master spi?

    CONVST_SAR State  = 0, Format1 = 1, Format0 = 0,  As I understand this is

    still SPI output but the device is the master.

    What is the difference between the SPI output and DOUT0?

    As of the moment, we are trying to figure out on how are we going to

    configure the AD7770 so that we can get 256 data points per cycle on a 60Hz

    AC signal.

    Can you give me some tips on which registers to set and its values so that

    we can achieve that?



    On Thu, Sep 8, 2016 at 4:18 PM, musach <