13 Hz interference seen on SPI of EVAL-SDP-CH1Z

Hi Janine,

The SPI comes directly from the SDP-H1 FPGA. It looks like it goes directly to the AD7779 - no buffering or level translation. I think the only answer here is that the SDP-H1 has been damaged somehow. There aren't any dedicated test points to try to debug how or where, but if the SPI transactions from the ESP32 work as expected and the SDP-H1 behaves as shown in the customer's photos then it seems there is some electrical issue with that SDP-H1. I'm aware that the SDP-H1 may be difficult to source right now due to a production delay.

Regards,

David

Hi David,

Thanks for the confirmation on SDP issue.

I'm trying to do some sort of level shifting with transistors in order to get the signals back in the right format. This transistor is actually going to be between the SDP and ADC board by removing the jumper resistors.

The problem is that the SPI clock frequency can't be modified, I assume it's fixed in the FPGA, therefore switching in this speed and keep the signal fidelity well is a bit tricky with my current general purpose transistors. I have to order some high speed components to achieve this.

Best,

Hadi

Hi David,

I fixed the communication issue. As you mentioned the GPIOs of the Spartan6 were somehow broken. I removed the jumper resistors on SL15 to SL18 on the AD7779 eval kit and filled the gap with my comparator circuit. I put this circuit between the SPI lines of two boards(SDP-H1 and AD7779) and it gave me a very clean SPI signal on all 4 lines(SDO, SDI, CS, and SCLK). 

I guess there is something wrong either with your Evaluation software or the SDP-H1 board that I have in hand.

Even with this clean SPI signals, I can't write to any registers with the eval software and SDP-H1.

By writing for instance 0x64 on 0x11, the GENERAL_USER_CONFIG_1, nothing changes and I don't even see a writing sequence but reading sequence on the oscilloscope SDI, and SDO.

As I already mentioned that to Janine in the previous discussion, I had a proper W/R transaction with my own MCU and the AD7779, and that's why I'm considering the SDP board the problem.

Best,

Hadi

Hi Hadi,
The evaluation board/software has existed for many years. Janine would be the expert on that, but in my opinion the balance of probability is that the SDP-H1 is the issue here. Even with the comparators to fix the levels, there may be some timing problem.

If you can source another SDP-H1 (and your budget etc allows for it) that will, most likely, resolve the issue. Production of the SDP-H1 has struggled to keep pace with demand unfortunately.

Regards,

David

Hi David,

Thanks for the quick reply!

Unfortunately, the board is so expensive and we can't give it another shot.

We just ordered this board to speed up the evaluation procedure, but it slowed us down in practice. Nevertheless, we started to develop our own FPGA to readout the Sigma-delta channels.

Best,

Hadi

Hi Hadi, sorry to hear about the delay due to this.
Newer parts will have more open source software collateral and support for open market controller hardware. Selected existing device families will also also be updated in terms of evaluation solutions and software resources. 

It looks like the AD777x family has benefitted from some of this, I can see source code for HDL - AD777X-ARDZ HDL project — HDL documentation. I haven't had much opportunity to use the FPGA based solutions, but if you have any general  questions regarding the AD7779 + FPGA, I'll try to find somebody to answer them and hopefully win back some of your lost time.

Regards,

David

Hi DavidORiordan , and JEstayo , 

So far we know the SPI pins are broken, however, I noticed by clicking the SD sampling in Evaluation software, that the Sigma Delta ADC channels data are graphed. I applied a sine wave to ensure it was a proper reading and it was all good, although I see some glitches.

1. Does that mean even though we're in SPI mode (FORMAT0 and FORMAT1 are tied to IOVDD), the FPGA is reading back the SD ADCs from DOUT pins?
2. I know the pin control mode isn't supported in Rev. H of the eval software. But would you tell me the steps to read back the SD channels in pin control mode in addition to configuring FORMAT and MODE pins? Do I also need to apply a clock on the DCLK pin, and then initiate the readback by toggling START, or any other pin is involved here? sorry for the confusion.

Best,

Hadi

Hi cdcdVDVdV ,

Please refer to the answers below. 

1. Yes. By default, the FPGA reading the SD ADCs conversion data from the DOUT pins (ADC DATA SERIAL INTERFACE) You can configure this by following table 17 in the datasheet.

How you configure or control the ADC is either by Pin control mode (level of the mode pins) or SPI mode (writing to the registers). in SPI Control, this option allows access to the full functionality of the AD7779.

2. You will have to provide sufficient SCLK if you plan to read the SD conversion over SPI. DCLK will not be needed in this case. The eval software, by default, reads the data from the DOUT pins. If you try to set the device to Pin control mode, and retain the SD conversion in the DOUT pins, the eval SW will still work.

Initiating a sync pulse on the START pin or SYNC_IN pin, will generate internal reset of the digital block. Apply this pulse in 2 cases (I'm taking the bullets below from the datasheet)

• After updating one or more registers directly related to the sinc3 filter. These are power mode, offset, gain, and phase compensation.
• To synchronize multiple devices, the pulse in the SYNC_IN pin must be synchronous with MCLK.

I hope this clarifies your questions.

*I have edited my answers. Please ignore the content of the first email notification you received.

**for ADC related questions, I suggest going back to the original thread ((4) Unable to configure on AD777x evaluation software - Q&A - Precision ADCs - EngineerZone or posting in (+) Q&A - Precision ADCs - EngineerZone

Thanks,
Janine