The SDP-H1 manual says that a pin is reserved to trigger and control the FPGA, as shown in the picture, then how should I use this pin to trigger the FPGA, my purpose is to achieve the function that the FPGA will output only when the trigger comes?
The SDP-H1 manual says that a pin is reserved to trigger and control the FPGA, as shown in the picture, then how should I use this pin to trigger the FPGA, my purpose is to achieve the function that the FPGA will output only when the trigger comes?
Hi APTX4869321,
While this functionality is provided in theory in general, whether it is available in practice depends on your specific application.
The applications engineer assigned to the evaluation board you are using may be able to answer if this functionality is available/applicable to your board and the associated ACE plugin. You will need to ask your question in the forum for the part you are working with - High-Speed ADCs - EngineerZone (analog.com) or High-Speed DACs - EngineerZone (analog.com), and include the part number of the device you are evaluating - "AD1234" for example.
Regards,
David