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SDP- H1 changing SPI clocking speed.

Category: Hardware
Product Number: EVAL-SDP-CH1Z being used with EVAL-AD4020FMCZ
Software Version: Latest SDP driver version available from AD EVAL-SDP-CH1Z product page, 24-07-2023

Hello SDP support.

I am using the SDP-H1 board with the EVAL-AD4020FMCZ daughter board and it working the way it was designed to do.

Because I am instrumenting a HV power supply unit (18kV @ 2A), I have a developed a FMC-Optical Fibre-FMC interface that sits between the SDP-H1 and the AD4020FMCZ, the FRU contents have been copied and placed on the SDP-H1 side of this interface in order for the SDP-H1 to still think it is directly coupled to the AD4020FMCZ which actually sits on the other side of the fibre optics, this interface is supposed to take the SPI bus into optical domain and back out again. The spoofing of the ADC eval card works, I ran into a problem with the clock speed of the SPI interface.

I am using Broadcom 2426Z FO-TTL receivers and 1624Z FO-TTL transmitters with some glue logic, these a very capable FO RX-TX pair with speeds up to 50Mbaud.

I can easy control the sample rate (we only require 10ksps, its a DC PSU) from ADI's GUI software for this evaluation board combination, but the speed of the SPI interface always runs at "full chat" the maximum possible speed for the AD4020 (which is approx. 96MHz). This SPI clock speed is too fast for my FO SPI HV isolation link, I need to slow it down for the to work with the Broadcom FO parts I am using.

BTW: The SPI clock speed we use for our HV PSU instrumentation cards is nominally 2.5Mhz - but we have been known to push this up to 10MHz.

Is there anyway way of telling the SDP-H1 to run the SPI interface at a slower clock speed?, maybe by editing the contents of the FRU memory to recognise a slower device.

Best Regards


PS: Thank you for the replacement SDP-H1 controller board.

  • Hi Danny,

    I'll have to look into it. Typically the software provided is "as is" and while it works for evaluation, it doesn't always suit prototyping.

  • Hi Danny,

    The expert on the AD4020 evaluation solution isn't available this week, I'll try to get his input on this when he is available.

    Regarding alternatives, there are the Linux drivers, FPGA HDL and "No-OS" resources available as previously mentioned. I've had a quick look at them and they all seem to assume the user will be using SPI at "full chat" - you would have control of the SPI clock but they all seem to have a dependency on a high speed SPI engine which might limit you to a Xilinx FPGA platform, eg Zedboard. If you wanted to run at lower speeds and use a microcontroller or a lower spec Linux board you might be able to use those resources as inspiration though.



  • Hi Danny,

    I've spoken to the AD4020 applications team - as I predicted the evaluation solution is just meant to be used as it is. I understand that you may have expected more from the SDP-H1. We are working on making new solutions that work for evaluation AND prototyping, with more portable and open software/firmware. The Linux drivers and FPGA HDL available for the AD4020 are part of that - it's just that the evaluation solution was developed and released long before that.