Hello SDP support.
I am was using the SDP-H1 board with the EVAL-AD4020FMCZ daughter board and was doing what it was designed to do.
The next day I powered up my test setup in the usual way, everything was preconnected ready to go.
The development laptop did not recognize the SDP-H1, even after several attempts following the instructions in UG-502 (just the SDP-H1 & EVAL-AD4020FMCZ were connected to the dev laptop). SDP-H1 said “No” – laptop didn’t register a USB device plugged in.
I changed laptops, reinstalled SW and changed USB leads – still No-Go with the SDP-H1.
So I started to debugged the SDP-H1, the schematic in the current UG-502 is different with regards to my version of SDP-H1 (ver1.4 2017, Serial No 21148415), it made life hard with respects to debugging some parts of my SDP board.
The SW for the AD4020FMCZ continually asks me to “rescan” because it can’t see the SDP-H1 as a registered USB device.
Results of my debugging exercise :-
CLOCKS Present and correct levels.
Power Supplies and enable signals around the SDP-H1
+3.3V_SWITCHED, No – No enable signal from U29 (OR gate of VIN_SDP_CON with BOOT_COMPLETE, neither of which were Logic Hi)
VCC_SWITCHED, No – uses same enable signal as above
VBUS present when plugged into laptop.
Not_POR does what it is supposed to do.
BOOT_COMPLETE = 0V, BF originated signal via an external latch U19.
FMC_POWER_EN = 0V, FPGA originated signal.
3V3_FPGA_VCC0, Yes correct voltage within tolerance.
2V5_FPGA, Yes correct voltage within tolerance.
VADJ_EN = 0V, FPGA originated signal.
VADJ_FPGA = 2.49V, enabled via DDR2_PWR_GD
1V8_DDR2_VDDQ, Yes correct voltage within tolerance.
0V9_DDR2_VTT, Yes correct voltage within tolerance.
0V9_DD2_VREF, Yes correct voltage within tolerance.
1V23_FPGA_CORE, Yes correct voltage within tolerance.
+12_VIN, Yes of course
FPGA_2V5_PWR_GD = ???, probably couldn’t find a component with known RefDes to probe (not all components have and RefDes on silkscreen and no component layout guide in UG-502)
DDR2_PWR_GD = 4.54V
+12_VIN_SWITCHED, Yes – the schematic for this in UG-502 differs from the components used for it on my SDP-H1.
+5V, Yes correct voltage within tolerance.
VADJ_EN=0.0V, FPGA originated signal.
The FMC power supplies do not seem to get enabled, because the FPGA never gets programmed.
BOOT Memory U701 activity.
BOOTMODE 0x3, Yes.
BF is trying to boot from SPI memory.
Activity on Not_SPISEL, SCK, MOSI and MISO.
Pulls ups working on the Not_SPISEL and MISO lines.
Following the schematic diagram, I have gleaned an understanding of how this SDP boots.
No USB detect, therefore no Blackfin comms and thus the FPGA does not get programmed, and hence no FMC power supplies enabled.
FMC_POWER_EN (from FPGA)
No VADJ_FMC as it does not get Enabled by FMC_POWER_EN
Although +12_VIN_SWITCHED is up and it is according to the schematic in UG-502 enabled by the same signal FMC_POWER_EN
If VADJ_FMC is powered up, that would generate FMC_VADJ_PWR_GD
FMC_VADJ_PWR_GD would enable 3V3_FMC
If 3V3_FMC is powered up, that light the FMC_ PWR_GD LED.
I believe the BLACKFIN F/W has been bricked somehow, apparently the F/W gets updated every time the SDP is used (info from SDP WiKI).
How do I get this board to work? I believe I may need to do a recovery or re-FLASH the F/W via the BLACKFIN JTAG port.