I have a ADF5902, I want to setup CLK1. But it's Register 7 have follow description:
"The CLK1 value sets a divider for the VCO frequency calibration. Load the divider such that PFD frequency (fPFD)/CLK1 is less than or equal to 25 kHz.
For example, for fPFD = 50 MHz, set CLK1 = 2048 so that fPFD/CLK1 < 25 kHz. "
fPFD/CLK1 must less than or equal to 25kHz ?
If it must be less than or equal 25kHz, timer = CLK1 x CLK2/fPFD is not less than 40us. The timer is too long.