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I am using single talise chip in my design. DO I need to call TALISE_enableMultichipSync() API function and what its return value means?

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  • so just to be 100% clear on this : the multi-chip sync function is not only meant to be used with 'multiple-ADRV9009'? It should also be used to 1x ADRV9009 connected to an FPGA through JESD?, to get the latency between 1 ADRV9009 and the FPGA fixed between different 'power-cycles' or JESD (re)connects?