Products Mentioned

ADRV9009 Recommended for New Designs
The ADRV9009 is a highly integrated, radio frequency (RF), agile transceiver offering dual transmitters and receivers, integrated synthesizers, and digital...
Datasheet
ADRV9009 on Analog.com

Thread Details

  • State Not Answered
  • Replies 1 reply
  • Subscribers 4 subscribers
  • Views 268 views
  • Users 0 members are here
Options 

        

            Post
             Go back to editing
        

    

    


    

    









		


















	
	
			
	
			
		
	
	
		

	    
	    
	    		
Phase synchronization not working with recent API

		
	
				

			

									
					    tcachat
					
							

            
            			
				
									
											
			
			
				
    
			
			
			    	
			                    
                
				                on Nov 4, 2024 
				
			
			
		
    
		
		                     
				
        		
    
		    
		    		    
    
		      		            		        
    Category: Software
    
    		        		            		    
    Product Number:  ADRV9009  
    
    		        		        		        
    Software Version: API 3.6.2.1
    
    		    		    
    
		    		    
		    			
    
			    
    We have custom boards with ADRV9009. We need to have a known phase between the reference clock and the RF output. We have achieved that following
    

    https://ez.analog.com/rf/wide-band-rf-transceivers/tes-gui-software-support-adrv9009-adrv9008-1-adrv9008-2/f/q-a/122649/talise_enablemultichiprflophasesync-and-talise_enablemultichipsync-which-order
    

    In other words it is working with following revisions:
    

    Talise: Device Revision 192, Firmware 6.0.2, API 3.6.0.5
    

    But it is not working with a newer version:
    

    Talise: Device Revision 192, Firmware 6.2.1, API 3.6.2.1
    

    Why is it so? What are the differences between the versions?
    

    Side remark: TALISE_enableMultichipRfLOPhaseSync is still not mentioned at all in UG-1295, as far as I know.
    
			
    
			
									
		                             
                        

    
    
                                            
                 software
                
                                                    
                 adrv9009
                
                                                    
                 API 3.6.2.1
                
                                                    
                 Wideband Transceiver IC
                
                                                    
                 phase
                
                                        
                                            
                
                
                                
                    Show More
            
    
    
    
		
    

				
				        
        		
    
			
						
									
												
			
			
                        
                                    
                        
                        
                        
            
			            
						
						
			
			
			
			
		
    

        
        
        
    
					
    
			
    


    
















    
	
    
	
    
					



			


				
	









	
      
	

    • 
	
      



	
		
	
	



      
	
      
		
      
							
					
      
		
      
		    
		    		    
			
				
									
							        
			
			
			
      •  Analog Employees  
      
            
						
                            
            
            				
            
                on Dec 9, 2024 1:14 AM
            
            
						
			            		
      
		
										0
					
	
      

		
		
      
		
      
                                
                                                            
      
					
      It should be working with the latest version as well. The UG-1295 doesn't have these details mentioned, you can see the below API definition from source file package.
      

      /*From source file package*/
       * \brief Sets up the chip for multichip LOs Phase synchronization
      LOs on multiple chips can be phase synchronized to support active antenna system and beam forming applications.
      

      This function should be run after all transceivers have finished the TALISE_setRfPllFrequency(), and before TALISE_runInitCals().
       * When the enableDigTestClk parameter = 1, this function will reset the MCS state machine in the Talise device and switch the ARM to run on device clock scaled instead of HSDIGCLK
       * When the enableDigTestClk parameter = 0, this function will enable Mcs Digital Clocks Sync and JESD204 sysref,
       * switch the ARM back the HSDIGCLK.
       * Typical sequence:
       * 1) Initialize all Talise devices in system using TALISE_initialize(),load the ARM and stream processor
       * 2) Set the RF PLL frequency with TALISE_setRfPllFrequency
       * 3) Run TALISE_enableMultichipRfLOPhaseSync with enableDigTestClk = 1 before TALISE_runInitCals()
       * 4) Send at least 4 SYSREF pulses
       * 5) Run TALISE_enableMultichipRfLOPhaseSync with enableDigTestClk = 0
       * 6) Send at least 4 SYSREF pulses
       * 7) Continue with init sequence ...Run initCals, bring up JESD204, etc
       *
       * \pre This function is called after the device has been initialized, ARM is loaded and PLL lock status has
       * been verified

       * \param device is a pointer to the device settings structure
       * \param enableDigTestClk =1 will enable/reset the MCS state machine and switch between device clock scaled and
       * HSDIGCLK

      uint32_t TALISE_enableMultichipRfLOPhaseSync(taliseDevice_t *device, uint8_t enableDigTestClk
      

      Do you see any error while enabling phase synchronization , can you please share us the error log and observations in detail.
      

      Can you please share us the test setup diagram as well.
      
			
      

		
			
	      

		
		
	
      
	
      
		
      
			
		
      
	
      
	
      
		
						
						
				
						
				
				
		
		
      
			
		
      
	
      

      

      •