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Inconsistent Phase on Startup

Category: Hardware


I am trying to test the RFPLL Phase Sync functionality of the ADRV9009. Right now I am comparing the phase between Tx1 and a signal generator outputting a continuous wave. The phase difference between the two is inconsistent between initializations when the RF PLL is not at an integer multiple of the device clock. I have the RFPLL Phase Sync set to Init and Track Continuously in the Evaluation software, and I believe I am using the most recent version. Any explanation as to why this may be occurring? 


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  • I would like to confirm that the relative phase between the two is consistent between initializations. I am following Figure 66 from the user guide with the only difference is using an oscilloscope instead of a VNA to compare the relative phase between the TX and Signal generator. I would like to recreate the plot in Figure 68.

    My current GUI settings are as shown below. I am transmitting a tone with a 0MHz offset from the RF LO.

  • Are you giving the same REF_CLK input source to both the eval boards? If yes, connect the REF_CLK output to the oscilloscope and also the TX1 outputs of both the eval boards, and then check the phase of the TX channels of both the boards w.r.t the REF_CLK signal.