The overload behaviour of the receiver ADCs in the ADRV9008-1 and ADRV9009 devices appears to be quite erratic. The PFIR filter is able to be modified such that it will saturate before the ADC overloads, which seems to signify that the resultant output is caused by the ADC itself. The attached plots from the Talise gui show a large signal that is causing an overload, which rather than saturating, appears to drop back to around zero. Is there any further information available as to the handling of the bit growth through the various decimation filters following the ADC? is there more than 16 effective bits through the ADC and filter chain or are they limited to 16 bits through each filtering stage? Is there any way to change the ADC behaviour to saturate rather than the wrapping behaviour as is seen in the image below?