TALISE_enableMultichipRfLOPhaseSync and TALISE_enableMultichipSync: which order?

Yes.You can follow the sequence.

Thank you for your answer. Nevertheless, I did not manage to get any better result. I can give some details:

From a situation where mcsStatus equals 0xB (returned by TALISE_enableMultichipSync(&talDev, 0, &mcsStatus);) :

If I call TALISE_enableMultichipRfLOPhaseSync(&talDev, 1); I get mcsStatus to zero, then after some SYSREF pulses mcsStatus is 0x8.

Then if I call TALISE_enableMultichipRfLOPhaseSync(&talDev, 0); I get mcsStatus to zero again, and after some SYSREF pulses mcsStatus is 0x3.

I never get 0xB again, except if I call TALISE_enableMultichipSync(&talDev, 1, ...) and send some SYSREF pulses again.

I have never seen bit 2 of mcsStatus active (0x4). On some other discussion I read that it was right to get 0x3 after PhaseSync, but I would expect to get 0xF.

I have two ADRV9009 that receive the same REFCLK, and SYSREF pulses. I can watch the RF output of both boards on the scope, the phase difference is (temporarily) constant, but random after each power up.

I have tried many different startup sequences. I have never seen the phase being slowly "corrected".

Is there restrictions on the period of the SYSREF pulses ?

Please refer below screenshot from help file for the sequence for running the RF PLL phase sync on ADRV9009.

Please refer below ezone post for additional information,

https://ez.analog.com/wide-band-rf-transceivers/tes-gui-software-support-adrv9009-adrv9008-1-adrv9008-2/f/q-a/115831/adrv9009-mcs-and-rf-pll-phase-sync-question

https://ez.analog.com/wide-band-rf-transceivers/design-support-adrv9008-1-adrv9008-2-adrv9009/f/q-a/122488/adrv9009-multichip-sync/365689#365689

Dear PVALAVAN,

 I would like to have a single initialization sequence, not two sequences that I have to merge in some way. My current code is based on the "headless.c" file provided by TES. Where exactly do I have to insert the calls to TALISE_enableMultichipRfLOPhaseSync in this initialization code? Everything I tried so far failed. Do I have to change the order of initialization significantly? Can we imagine that some day the TES will produce a code with TALISE_enableMultichipRfLOPhaseSync (possibly in a comment)?

What do you thing of the values I mentioned 4 days ago? (0xB, 0x3, 0x8). Is it right to expect 0xF?

In the mean time somebody points me a demo board with two ADRV9009:

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms8-ebz

What is the initialization code of this board?

Thank you

Please post in FPGA Reference design forum for queries related to Fmcomms8.

For details on Two ADRV9009 please refer below link,

https://wiki.analog.com/resources/eval/user-guides/adrv9009-zu11eg?s[]=adrv9009&s[]=zu11eg

For PLL Phase sync, Please follow the below sequence.

1) Change the rfpllphasesync mode to init and track

2) Insert the below new MCS sequence in the device initialization sequence explained in UG.

3) 

Dear PVALAVAN, thank you for your precise answer. Unfortunately, I did not get any better result. It was essentially the sequence I used (and the sequence from TES). Do you have an idea why mcsStatus is 0x3 after calling TALISE_enableMultichipRfLOPhaseSync? (see my post above)

PllLockStatus is 7, which is good I think.

Can you please share the block diagram of your setup particularly showing your reference clock distribution and sysref distribution between different ADRV9009 and baseband?.

Are you using singleshot or continuos sysref?

Please refer to UG-1295 for phase sync evaluation with 2 ADRV9009 EVBs.

tcachat said:

I have never seen bit 2 of mcsStatus active (0x4). On some other discussion I read that it was right to get 0x3 after PhaseSync, but I would expect to get 0xF.

MCS Status 0XF is not possible as we are not using CLKPLL SDM sync.

Dear PVALAVAN,

I have tried both TAL_RFPLLMCS_INIT_AND_1TRACK and RFPLLMCS_INIT_AND_CONTTRACK.

You say I cannot have mcsStatus equals 0xF, but is it right to have 0x3 at the end of the procedure? (whereas before caling TALISE_enableMultichipRfLOPhaseSync, I have 0xB)

I have changed my LO frequency to 307.2 MHz, hopping to simplify the situation (my REFCLK is at 153.6 MHz). Then I tried a few times, and it seems that the phase difference between both ADRV9009 can be any multiple of 90° (randomly), so I did not manage to synchronize them better.

Is there a way to know whether the LO synchronization succeed? Took place?

Figures 68 and 72 from UG-1295 let me think that the transceiver is already in RadioOn state when the LO synchronization process begins. Is it right?

What is the fastest way to change the LO frequency and start a new synchronization process? Preferably without changing JESD settings.

Thank you in advance

I have now some new results. I have observed on the scope, shortly after going to RadioOn state, that the phase difference between both boards is adjusted, because I am sending SYSREF pulses every second, and using TAL_RFPLLMCS_INIT_AND_CONTTRACK. I can go to RadioOff, then RadioOn, and after the SYSREF pulse I come back to the same phase difference, which is good. But when I Power Down and then PowerUp the ADRV9009, the new phase is random. I have to check my REFCLK in that case.