Hello,
I am using custom board with ultrascale+ and muti adrv9009.
I need to use MCS and RF PLL phase sync function.
The software that I use is no-os example( I modified for muti chip) and Firmware is 6.0.2, API is 3.6.0.5.
Refer to UG1295 and API manual, I did some tests and got results as list:
1. Just run TALISE_enableMultichipSync(), and .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC.
Result : After TALISE_enableMultichipSync, I get MultiChipSyncStatus,the SyncStatus value is 0xB. Look muti TX Singal on the oscilloscope, RF PLL Phase Sync is not sync.
2. Run TALISE_enableMultichipSync(), and set .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC.
Result : same as test 1.
3. Just run TALISE_enableMultichipRfLOPhaseSync(), and set .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC.
Result : After TALISE_enableMultichipSync, I get MultiChipSyncStatus,the SyncStatus value is 0x3, JESD Link Status error.
3.Set .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC, run TALISE_enableMultichipSync() first, then run TALISE_enableMultichipRfLOPhaseSync() , and set .rfPllPhaseSyncMode = TAL_RFPLLMCS_INIT_AND_SYNC.
Result : After TALISE_enableMultichipSync, I get MultiChipSyncStatus,the SyncStatus value is 0xB, after TALISE_enableMultichipRfLOPhaseSync() , the SyncStatus value is 0x3, JESD Link Status OK, RF PLL Phase is synced.
So,
1. Should I use both TALISE_enableMultichipSync() and TALISE_enableMultichipRfLOPhaseSync() for mcs and RF PLL sync?
2. why does TALISE_enableMultichipRfLOPhaseSync() reset Device Clock divider Sync Status? Does this have any effect to msc ?