The datasheet says the frequency of the clock input (the REF_CLK_IN_x pins) must be between 10 MHz and 1000 MHz. However, referencing the Hardware Reference Manual UG1295, Table 41. taliseDigClocks_t Data Structure Description, the deviceClock_kHz field is listed as having only 3 permissible values. In my testing I have used a device clock of 307.2 MHz and things seemed to work, at least as far as the JESD interface was concerned. So it seemed that this table was perhaps just a suggestion until I tried a strange frequency. I cut the device clock, the PLL VCO Frequency, and both RX/TX sample clocks to 90% of their previous values (307.2 MHz/12.288 GHz/307.2 MHz/307.2 MHz respectively) to see if things would still work. All was fine, JESD lanes came up, no errors reported in the profile, etc. until I set the RF PLL frequency. I had been setting it to 2.000 GHz but after the frequency reductions, the center frequency on the spectrum analyzer moved to 2.222 GHz. I can see mathematically how setting the RF PLL to 2.0 G and getting 2.222 G out can be represented as a ratio 1/0.9, but how does this happen? The requested RF PLL frequency is sent to the internal ARM processor as a plain 64-bit value and there doesn't appear to be anything in talise_config.c that could account for this ratio error.
Bottom line, in our application we would like to be able to set an arbitrary device/sampling clock to avoid doing resampling during post processing. Is this possible or do we need to stick to specific frequencies?
Secondarily, if we have frequency freedom, why is the RF PLL frequency wrong?
