Introduction
This section describes how a signal is processed by a Transimpedance Amplifier (TIA) , Analog-to-Digital Converter (ADC), and Half-Band filter (HB), and how this affects the triggering of analog and HB peak detectors.
Figure 1. ADRV9001 Rx Chain
Figure 2. ADRV9001 Rx Chain and Frequency Response
Figures 1 and 2 illustrate the receiving (Rx) chain of a system. Figure 1 provides a block diagram overview, while Figure 2 details the signal's journey through key components showcasing the working of peak detectors. As shown in Figure 2, the input signal, at a frequency equal to the Radio Frequency (RF) carrier plus the Intermediate Frequency (IF), is first processed by an analog mixer. This mixer shifts the signal down to the IF by combining it with a Local Oscillator (LO) signal matching the RF carrier. The resulting IF signal is then passed through the TIA, converting it from a current to a voltage suitable for the ADC. One must note that the TIA frequency response is like that of an LPF, which also attenuates signals outside the band of interes t. Then this signal is passed through the LPF which further attenuates the out-of-band signals. The user can configure the LPF within TES as shown in Figure 3.
Figure 3. LPF Configuration
The ADRV9002 offers selectable LPF orders:
- First-order: Reduces power consumption but provides lower image rejection.
- Second-order: Improves image rejection but increases power consumption.
Figure 4 illustrates the frequency response of both first and second-order LPFs. This information is also available in the user guide. The LPF primarily serves to prevent aliasing and is not intended as a substitute for external signal filtering.
Figure 4. RX LPF Frequency Response at Different f1db Configuration
Before the ADC an Analog Peak Detector (APD) is placed for monitoring the peak power of the signal entering the ADC. Here the APD monitors the signal peak power; once the signal is above the certain threshold value provided by the user, this results in a flag in the gain control block. Then ADC digitizes the signal for further processing. This digitized signal is passed through the Half-Band (HB) filter and at this stage the HB peak detector monitors the signal, which may again result in a flag in the gain control block. The gain control block (see Figure 1) uses a combination of the APD upper threshold and the HB peak detector upper threshold to decide the level by which the attenuation will be adjusted in the front-end attenuator block. The peak detector configuration can be done in TES as shown in Figure 5. ADRV9002 has the flexibility to control the external gain block as well.
Figure 5. Peak Detector Configuration
The HB filtering is determined by the system clock rate ((± 25*(System Clock))/184.32 MHz) and the system clock rate is depended on the profile. The frequency response of the filter is not given in the user guide. Instead, it is provided in a separate file: hb1.mat. The Figure 6 shows the filter magnitude response of HB filter for system clock of 150 MHz, 184.32 MHz and 200 MHz.
Figure 6. HB Filter Magnitude Response
Steps for Obtaining the HB Filter response using hb1.mat
- Load the file using the MATLAB Command: load('hb1.mat').
- We will see a set of data as shown in Figure 7.
Figure 7. hb1.mat Data
- The filter coefficients are stored in decflt_h.
- Now use the function fvtool(decflt_h) to get the filter response. The filter response looks as shown in Figure 8.
Figure 8. Normalized Frequency Filter Magnitude Response
- In the filter visualization tool, we see two options: one is analysis parameters and the other is sampling frequency as shown in Figure 9.
Figure 9. Filter Visualization Tool Options
- In the Analysis parameters, we can change the plot axis as shown below. In this case, the normalize frequency option will be unchecked
Figure 10. Analysis Parameter
- Once the above parameters are set, click on sampling frequency option and change the sampling frequency (Fs) to the system clock frequency (in this case, 184.32 MHz). The passband frequency is 25 MHz.
Figure 11. System Clock Rate
- The below figure shows the filter response
Figure 12. Filter Magnitude Response for System Clock Rate of 184.32 MHz
Please find the hb1.mat file.
