Q: STEP Model of Evaluation Board

A STEP (Standard for the Exchange of Product Data) file is a 3D model that can be used in most software suites that deal with 3D models. The 3D model of the Evaluation Board may be helpful to customers who are looking to design cases, mounts or any sort of physical attachment to the EVB. This model is extracted from the Allegro .brd file that is provided in the Design Files package available on the Product Page. ADRV9002_CE02B_063978.zip 3D View of STEP Model for EVB

Question 1

ADRV9001 Soldering / Reflow Profile

Accepted Answer

PDF 
 Source: STATS ChipPAC Application Notes fcBGA / fcBGA-H 19 March 2012, Rev 1 
 1) Introduction: 
 Flip Chip interconnection typically provides the ultimate in miniaturization, reduced package parasitics and enables new paradigms in the area of power and ground distribution to the chip which are not feasible with other traditional packaging approaches. STATS ChipPAC&rsquo;s high-end BGA Flip Chip packages include the fcBGA, fcBGA-SiP, fcBGA-H, fcBGA-MP and fcBGA-SS2/SS3. The fcBGA package is the main platform in this package sub-group, which also includes a thermally enhanced version with heat spreader (fcBGA-H) and a package subsystem meeting the standard BGA footprint that contains multiple components within the same package (fcBGA-MP). STATS ChipPAC&rsquo;s Flip Chip BGA packages are available in ball counts ranging from 220 to 3213, body sizes from 12 x 12mm to 55 x 55mm and various package formats. STATS ChipPAC offers full turnkey services ranging from design through production, including high speed, high pin count digital and RF testing. 
 
 2) PC Board Design Guidelines: 
 The fcBGA is compliant with JEDEC MS-034. IPC-SM-782 usually dictates the guidelines by which the PC Board (PCB) pattern should be designed. Working with an Electronics Manufacturing Service provider and/or PCB design house with experience designing and mounting this package type is recommended. The following guidelines are offered based on best known practice at the moment based on STATS ChipPAC evaluations and research. JEDEC MS-034 Compliant: 1. Package Height: &bull; fcBGA: 1.17, 1.35, 1.56, 1.76, 1.96, 2.03, 2.13, 2.33 and 2.45mm nominal thickness &bull; fcBGA-H: 1.35, 1.47, 2.52, 2.92, 3.0 and 3.10mm nominal thickness &bull; Package height typically varies with body size, ball size, substrate layer count, die thickness, heat spreader, etc 2. Package Size: 12x12mm to 55x55mm 3. BGA Ball pitch: 0.5mm (small body, thin profile), 0.8mm, 1mm (typical pkg platform) The fcBGA package is primarily composed of an ABF buildup substrate with BT core. This adds stiffness to the package and uniform expansion during board mount and board level temperature cycling. Also, because of the flip chip die up configuration, the solder balls for this package are typically placed in a complete array over the entire bottom side. Therefore, balls immediately under the die may be used as thermal paths to further enhance the thermal performance. 
 PCB Land Pattern and Solder Mask Design: A typical package outline and appropriate tolerances are shown below. The solder lands on the package side are always Solder Mask Defined (SMD). The land pattern on the PCB should be designed according to solder registration opening size (SRO) on the package as shown in the table below. The land on the PCB should be Non-Solder Mask Defined (NSMD) in order to realize the best board level reliability performance. The diameter of the solder ball land on the PCB should be the same or up to 20% less than that of the package substrate solder land. Designing PCB land diameter equal to that of the substrate is quite common, however, making the NSMD land pad on the board a little smaller can increase the stand-off and can increase the board level reliability. The solder joint during board level temperature cycling will typically fail at the solder ball to package substrate interface if the lands are the same size; slightly decreasing the PCB pad land will not cause failure to shift to PCB to ball interface and may positively impact the number of cycles before the solder ball to substrate interface fails. The trace leading into the NSMD ball land on the PCB should not exceed more than 50% of the land diameter. Again, this is to avoid too much solder wetting of this lead-in to the ball, thereby creating too much ball collapse and possibly impacting board level reliability. 
 
 PCB Thermal Via Design: &bull; The flip chip die up configuration of the fcBGA package thermal vias in PCB design provide an effective method of improving the thermal performance. &bull; Thermal performance is typically dependent on package size, die size, substrate layer and thickness and solder ball configuration. Thermal simulation for specific package applications should be performed to obtain more reliable thermal performance of package. Thermal performance data of typical package configurations are listed below: 
 
 3) Board Assembly Guidelines: 
 Most reputable EMS providers have their own rules, guidelines and standard practice regarding mounting surface mount packages in general and the fcBGA type package in particular. However, the following guidelines and principles have been characterized and proven to result in a reliable board assembly: 
 Stencil Design: 
 
 Laser cut stencil with electropolished walls is recommended. 
 Aperture size to PCB pad size is typically 1:1 ratio with .125 to .150mm thick stencil. 
 For 1.0mm pitch, aperture can be increased to be 0.05mm bigger than PCB pad size and made square to increase solder volume (increasing stand-off), if necessary. 
 
 Paste and Reflow: 
 
 Water soluble or No-Clean paste can be used (Type 3).
 
 37%Pb-63%Sn eutectic paste 
 Sn-3%Ag-0.5%Cu lead-free paste

The reflow profile depends on the thermal mass of the other packages on the board. The fcBGA package will most likely be one of the higher mass packages on the board. Internal studies have shown good results when using the following reflow guidelines based on the solder paste used:
 
 For eutectic SnPb paste: The reflow peak temperature should be kept in the 215&deg;C to 225&deg;C range. An actual reflow profile used to produce good board level reliability result is shown below (no clean paste): 
 
 For Pb free paste: The reflow peak temperature should be kept in the 225&deg;C to 245&deg;C range. An actual reflow profile used to produce good board level reliability result is shown below (no clean paste): 
 
 No Clean pastes typically have shorter reflow profiles and dwells as the alcohol based solvent activates rapidly. Follow the paste manufacturers recommended profile and application notes. Also, no clean pastes have flux that is typically less active, so reflow in a Nitrogen environment (<75ppm) may be advised.

Rework: 
 
 The fcBGA type package is relatively easy to rework due to high package stiffness. 
 Bake board at 125&deg;C at least 2 hours prior to part removal. 
 Make sure board is flat to avoid tilting and improper removal that could cause bridging of solder. 
 Because of the mass of this fcBGA package, under board heat is not normally required, although may be necessary for the 31mm square packages and above. Where underboard heating is required maintain approximately 120&deg;C. 
 Make sure hot gas nozzles are properly directed at part to be removed.
 
 PbSn: Peak temperature should be 200&deg;C 
 PbFree: Do not exceed peak temperature of 225&deg;C if possible.

Lift off part with integrated vacuum pick-up and clean the site properly with solder wick or alternative method. 
 On rework printer/placer, take care to properly align and print the same solder paste with a metal blade and the miniature stencil. 
 Properly place the new package within 0.15mm accuracy if possible and use the same reflow profile as used to initial mount package.

For more information on thermal characteristics of the IC package check out this article https://www.analog.com/en/resources/technical-articles/thermal-characterization-of-ic-packages.html

Question 2

ADS Simulation of Matching Networks

Accepted Answer

Introduction 
 In this guide we will go through some basics of simulation in ADS. This will primarily show you how to do your own RFIO matching simulations in order to fine tune components for your chosen baluns and operating bandwidth. You will need to be familiar with the ADS environment and have a basic understanding of transmission line theory . You will need access to the ADS simulation environment and S-Parameter files provided here for the Tx, Rx and External LO ports: 
 ADRV9002_S-Param_Files.zip 
 
 Introduction 
 The intention here is to put all the elements of the RFIO traces together to see the output s-parameters and then be able to tune them using different matching components to get preferred output response. The Rx will be used as an example here to show the main elements of the RFIO traces. Underneath the first flow chart is a more detailed version showing the differential lines. 
 
 Rx port s-parameters 
 These are measured off the ADRV9002 device and are provided for use above. These do require some manipulation to get into a format to be used and that is detailed in the next section. 
 Rx Laminate 
 This is another s-parameter file that is provided above and is the measured response from the laminate on the part. 
 Trace and Matching Components 
 This includes the trace lengths/widths between each of the ports and components and the components themselves. Ideally use the s-parameter component libraries from the manufacturer here. 
 Balun 
 This is chosen balun for the operating bandwidth. For details on how to wire up the balun in ADS read the s-param file in a text editor and the pin/port matching will be outlined in the header of the file. 
 Next step is to put these elements together in an ADS schematic. Starting with the Rx port s-parameters 
 Using the Rx port s-parameters 
 The Rx port files are in S1P format in the above download package. This file represents the differential RF port but it is formatted as a single port file. To get this into a differential port format that can be use easily for RF matching we will import the file as a DAC element in ADS and apply the following equations to it. Using a single differential port option for each input of the RF port will make all quality metrics of RF interfaces involving a balun readily available. This is the approach used to characterize a RF balun and we are extending the same method for the entire RF PCB board traces with matching network. Insertion loss, amplitude imbalance, phase imbalance as well as return loss is all metric quality for any network involving single to differential conversion. Imbalance quality is a important metric and should be known for the entire network involving single-to-differential conversion as it can cause RX/TX path impairments 
 Its important to note here that for this simulation I will be using Term 1 and Term 3 as the differential port side terms and Term 2 and the single ended port side term. Also on the Rx the reference impedance (Rref) is 100ohms. For the Tx and LO ports the reference is 50Ohms. 
 
 This equation manipulation is a reflection co-efficient conversion and now allows us to use the variable TX_SEDZ_SE for both of the differential ended ports. The s-parameters seen at each of the diff terms is going to be identical. Create a Term element in ADS and in the properties assign the variable TX_SEDZ_SE to Z.

Adding the Laminate 
 The laminate file is a 4 port file or an S4P format. This has two sides for the differential sides, port 1 and 2 on one side and port 3 and 4 on the other. Port 3 and 4 are connected to the Rx s-parameter ports and port 1 and 2 are connected to the board traces. It does not matter greatly which port (1 or 2) you connect to which Rx port term because the port terms are identical.

Traces and Components 
 Adding in the trace length and components is the next step. There are trace parts in ADS that you can add here. Make sure the dimensions of the trace are exactly the same as the trace on your PCB. Similarly there are ideal components in the ADS library that can be used for the matching network. You can start a feasibility study by running a simulation with ideal components and then start adding simple microstrip line (MLINE and the required MSUB settings too) between components. Length of these lines should be minimized such that there is no significant phase rotation introduced by traces. This will make it electrically small with respect to the wave length of signal that needs to propagate through the trace. Using the MLINE element you will generate a schematic similar to this: 
 
 For the ADRV9002 the matching networks were designed to be customised after manufacture. This was to enable to possbility for different baluns to be tried on the Evaluation board. as a result the matching network is dynamic enough to take various baluns and matches. This also let us extract the layout files and simulate the exact trace lengths of the board. This gives a much closer simulation as it takes the board stack-up and other factors into consideration as they are simulated. 
 How to extract them is beyond this tutorial but I will use the extracted trace simulations in the following sections. I have created a 'look-a-like' model to make seeing the schematic and placing the matching components easier.

Balun 
 Balun selection is important and will have the most impact on the final reflection results of the overall RFIO trace. The matching network of components is there to try and trim the balun response down to an acceptable level for the desired bandwidth. Some baluns have a center tap to accept DC current and others do not. This could be a consideration for your project, a balun with a center tap might need fewer components and be more reliable than powering the balun with DC from the differential traces. This selection will also affect your layout around the balun. On the ADRV9002 EVB we use RF chokes onto the differential lines to supply the balun with DC power. 
 The balun s-pparmeter file will be an S3P, S4P or an S5P in some cases. Figuring out how to wire up the balun is important and the details are in the header of the s-param file, the pins of the balun will be matched to a port of the s-parameters. Reference the Data sheet of the balun to make sure its connected correctly. 
 For example here I am trying out the balun on its own to see the s-param response matches the plots in the data sheet to ensure I have the connections correct. 
 
 Reflection Results 
 The smith chart of the output RF port (in this case Term 2) will show the reflection results. This is the S22, or return loss, and will show the phase and magnitude of the RF response over the simulation frequency in the S_Param design block. The phase imbalance and the magnitude imbalance are also important quality metrics to see in a differential trace. This and the S21 or insertion loss will need to be calculated as there is a differential trace involved. 
 
 These three equations allow us to plot the S21, the Phase Imbalance and the Magnitude Imbalance of the RFIOs. This now looks at the RFIO block essentially as a two port trace. These can then be added to the data display window. These results will now be used to get a baseline and to see the effects of tuning the matching networks. 
 
 Tuning the Matching Network 
 Tuning the matching network is a term used to describe changing the component values in the network to get the best response for the bandwidth of choice. This takes into account the type of network you are implementing (L or Pi for example) and the values of the components that make up those networks. Important to note that the Balun will have one of the biggest impart on the output performance than any other part of the RFIO. The matching network is there to improve the response of the balun and RF port. 
 On the ADRV9002 Evaluation board we have over designed the matching network to give flexibility for customers to use different baluns and tuning options. The evaluation board has what looks like a wide-band matching network that can be populated to be various L or Pi networks. This gives us ample opportunity to tune for various baluns and BW. 
 Initially its recommended to populate the network in ADS with ideal components from the basic component library. Assign roughly desired values to these components and simulate. The tuning tool can then be used to get better performance results. Open this tool and select the components in the matching network to add to the window. These can now be adjusted and min/max setting applied. increasing or decreasing the values on this window will have an immediate response on the Data Display window to show you he change in behavior of the network with the new values. This can be used to bring the freq of interest along the arcs of resistance and reactance to get it close to the 50Ohm center. 
 
 It can be helpful to try different variations of matching networks and different component types to get the best results. Often the smaller the value of capacitor or inductor will have the biggest impact on the reflections, the bigger the value the less effect they start to have. This can be used when you need to add DC blocking capacitors to the network without wanting to affect the matching performance, add big value caps. 
 When you have acceptable performance next use a component selection guide to see what values of real components are available to use and change the values you have set to the nearest real value that can be attained. Component manufacturers will usually have s-parameter libraries or files available for each of the components they sell, download these and use the real s-parameter components in the simulation next. 
 Murata example: https://www.murata.com/en-global/tool/data/librarydata/library-keysight2 
 
 You are now simulating the response using as many measured s-params as you can including the port, balun and matching components. 
 Recommendations 
 In the User Guide section titled RF PORT INTERFACE INFORMATION there are some more details about the RF port interface on the ADRV9002 and the evaluation board. This also includes a list of different baluns from various manufactures, covering different frequency ranges and the accompanying matching component values to give a good response. This is using the EVB layout, which can be used as a reference design, but can be a good start for components on a custom layout with the same balun. 
 Appendix: 
 To gain some confidence in your simulation environment before adding in trace lengths and components, compare your setup to this one and ensure you have the same data display plots. 
 This is using the example blaun from the above tutorial, the TCM2-63WX+ from Mini-Circuits, the Rx port and laminate s-parameters provided in this tutorial.

Question 3

STEP Model of Evaluation Board

Accepted Answer

A STEP (Standard for the Exchange of Product Data) file is a 3D model that can be used in most software suites that deal with 3D models. The 3D model of the Evaluation Board may be helpful to customers who are looking to design cases, mounts or any sort of physical attachment to the EVB. 
 This model is extracted from the Allegro .brd file that is provided in the Design Files package available on the Product Page. 
 ADRV9002_CE02B_063978.zip

3D View of STEP Model for EVB

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