Question 1

Automated TDD

Accepted Answer

These guides cover the functionality of the Automated Time Division Duplexing (TDD) tab found in the Transceiver Evaluation Software (TES) package provided with the ADRV9001 product range, as well as provides some starting tips to get Automated TDD setups off the ground. For full context on this guide it&rsquo;s best to also read the &ldquo;Produce and Compile Sample C99 Code&rdquo; guide found on the EngineerZone forum: https://ez.analog.com/wide-band-rf-transceivers/tes-gui-software-support-adrv9001-adrv9007/w/documents/15577/produce-and-compile-sample-c99-code . 
 A fully working Auto TDD setup can be deployed to either the Evaluation platform or to a customer&rsquo;s unique platform using the same procedure demonstrated in the &ldquo;Produce and Compile Sample C99 Code&rdquo; guide . It&rsquo;s also best to have read the Automated TDD material provided in the User Guide on https://www.analog.com/en/products/adrv9002.html . For reference, below is provided a block diagram of the setup being used for these coming examples: 
 
 Note: certain standards will have issues being captured cleanly on the Spectrum Analyzer without a trigger. A very good trigger for the Tx capture is the Tx_enable signal, which in the case of the ZC706 evaluation platform can be pulled to one of the available SMA connectors. More detail on accessing and directing ADRV9001 signals is provided in each individual chapter. 
 We&rsquo;ll begin by connecting to the device. Make certain before beginning that the correct SD Card image revision is loaded on the SD card. There are tutorials available on EngineerZone for: 
 
 Quick Start Guide: https://ez.analog.com/wide-band-rf-transceivers/tes-gui-software-support-adrv9001-adrv9007/w/documents/15490/quick-start 
 SD Card Imaging: https://ez.analog.com/wide-band-rf-transceivers/tes-gui-software-support-adrv9001-adrv9007/w/documents/15476/sd-card-image 
 
 More information can also be found in the User Guide section on EVB setup. 
 Certain considerations need to be made here, primarily that only TDD configurations are compatible with Automated TDD functionality. Frequency Division Duplexing (FDD) setups require that any signal chain in use is sending / receiving data constantly, meaning there&rsquo;s no time during which any signal chain can be powered down. 
 
 Always be aware of which version of silicon your setup uses, as well as the variant of evaluation board (W1 / W2). Each version of silicon and variant of eval board will come with constraints on what frequency ranges the board is optimized for and what performances are possible. Adjust your configuration to suit your evaluation board. 
 Given that there is such a large amount of flexibility provided by the Automated TDD functionality, we&rsquo;ll use multiple device configurations to go through as many of the configuration options as possible. 
 To give these examples some context, we&rsquo;ll attempt to implement some LTE 8 setups normally used in base-stations:

Above are shown 7 common configurations. We will cover enough of these, to show the depth of flexibility our platform provides. For those unfamiliar with the &ldquo;Uplink&rdquo; and &ldquo;Downlink&rdquo; terminology, here is a diagram which puts up/down link in terms of T/Rx: 
 
 As mentioned earlier, these configurations are being implemented from the base-station point of view, meaning the downlink slot will be used for Tx operation, and uplink of Rx operation. These configurations provide a great starting point for any user who is unfamiliar with Automated TDD functionality. 
 This guide will be broken down into chapters for ease of reading. Each configuration covered will be given its own chapter on this forum.

Question 2

Digital Pre-Distortion

Accepted Answer

Introduction to DPD 
 This tutorial will cover a brief intro on Digital Pre-Distortion (DPD), why its used and how it works. It will also cover how to go about setting up a DPD measurement, including running calibrations for losses in equipment and give two examples using different Power Amplifiers (PA). The data shown in this tutorial is from real in lab measurements. This tutorial is for anyone looking to implement or evaluate the performance of the ADRV9002 or ADRV9005 DPD feature. To follow along with the practical you will need an ADRV9002 evaluation platform, Transceiver Evaluation Software from the latest SDK, PA and accompanying attenuators and splitters based on your requirements (more on how to chose these below). 
 Digital Pre-Distortion 
 DPD is a feature that uses a real-time feedback loop to pre-distort data being transmitted through a power amplifier (PA). It's used in transceiver applications to generate a more robust linear signal for transmitting data, to keep within ACPR specifications for RF bands and to utilise the PA in its most efficient state to maximise power useage. The PA is most efficient in its compression region, as shown in Figure 1, where the signal gets non-linearitiese introduced as a result. DPD works by taking in the output of the PA, calculating the non-linearity and applying an opposite distortion to the signal before it is transmitted and reaches the PA. The sum of this pre-distortion and the PA distortion should output a perfectly linear signal. This allows the user to get the best performance out of the chosen PA, however each PA will have different performance even with DPD and will need to be fine-tuned. 
 For more in-depth understanding and debugging refer to the User Guide for all up-to-date documentation on the DPD and TES functionality.

Figure 1. PA Output 
 FAQ 
 
 What is the maximum useable bandwidth for the DPD? The maximum bandwidth for DPD on the ADRV9002 is 20MHz. This is based off 1/5th of the maximum internal Tx observation bandwidth of the DPD block, which is 100MHz. Using this much margin allows the DPD engine to correct some of the odd harmonics that will have the biggest impact on stability. 
 
 Setup for DPD 
 Measurements 
 The DPD engine requires both Tx and Rx signals to calculate the coefficients. The coefficients will be applied in the Tx signal (pre-distort). Shown in 
 
 Figure 2. DPD HW Setup 
 This setup means that for the user&rsquo;s implementation, one of the Rx channels will need to be permanently used as the DPD observation path. In the ADRV9002, this means the user can implement one of the following:

1T1R TDD with DPD

1T2R TDD with DPD

2T1R TDD with DPD

2T2R TDD with DPD

1T1R FDD with DPD

Figuring out what your hardware setup will include is the next step. To do this we would recommend starting with the frequency band your application is targeting, from there you will need to understand the link budget and how much power output will be needed from the transmit system. From this point you can start to look for a suitable PA for the system. When you have found a PA that will operate in the freq of interest and provide enough power you can determine the rest of the DPD feedback loop. Using the input power required to push the PA into the compression region you can determine if an addition gain block is needed before the PA as the output from the EVB will be between 5 and 7dBm max. The ouput power of the PA will determin how much attenuation is needed to bring the loopback signal down to the required -18dBm to the input of the ADRV9002. This will also help identify the power rating on the attenuators needed. 
 At this stage you will have a PA, attenuators, gain block and coupler/splitter chosen for the feedback loop. 
 
 Example 1 
 Equipment List 
 
 ADRV9002 evaluation platforrm 
 PC with latest TES 
 Spectrum Analyser 
 Signal Generator 
 Power sensor 
 PA / Gain block 
 RF cables 
 Attenuators 
 Splitter/Coupler 
 
 Calibration 
 Calibrating each piece of the feedback loop is very important to get the most accurate picture of what is happening in the loop and will help evaluate and stabalise the DPD. Calibration is pretty simple but time consuming as it involves using a signal generator and a power sensor to input a signal of good quality and know freq and amplitude into a cable or coupler and sensing the power on the other end of the part under test. The difference in power level through the part is the loss and should be noted. Running this calibraion at the freq uency of interest is important as the response of each part can change against frequency. 
 You can use the losses measured to fine tune the attenuation levels in the loopback. 
 
 Hardware setup 
 Shown in Figure 3 is a block diagram of the setup using the ADRV9001 evaluation board (EVB) Tx1 is the transmit channel. The Tx signal must first go through a filter to get rid of harmonics that may make the DPD unstable. The Tx signal is then passed through a simple Minicircuits gain block to increase the signal power level to be able to push the PA into saturation. The gain block is a fixed 40dB so we have the flexibililty on the ADRV9002 side to use the attneuation to set the initial power level for the loopback. The PA outputs around 40dBm so the attneuators next to the PA must be rated to be able to take the 10W of power. In this loopback there is a 20W 20dB attneuator followed by a 10W 10dB and then 2W 20dB to bring the power level down to -10dBm going into the coupler. The coupler also has its own losses that we have claibrated earlier. The cables also have a loss and the sum of these leaves us with -18dBm going into the Rx port on the EVB. There is a little bit of torrerance here, the power level to the Rx1B input should be -18dBm +-5dB for the DPD to operate correctly. This level is not user configurable. 
 The user needs to be aware of the kind of data being transmitted, for example if the data has a high PAR then the Tx data will need to be backed off enough so as not to saturate the DACs when the signal goes through the peak expansion (pre distortion). There is no crst factor reduction block in the ADRV9002, the user should be aware of this and make provisions to apply crest factor to all the signals being supplied to the ADRV9002 for transmitting. The importnace of this and other tuning methods will be discussed in the advanced DPD tutorial. 
 
 Figure 3. Simple Example DPD Block Diagram 
 TES setup 
 With this simple setup the user can then use the TES to enable the DPD. For more details on any of the steps below please see the User Guide section on Digital Pre-Distortion and ADRV9001 Evaluation System. 
 
 After successfully connecting to the FPGA, in the Configure tab select an LTE TDD setup.

Figure 4. Device Configuration 
 
 The external path delay will need to be calibrated. This can be done in the with the Python interface by loading the &lsquo;External_Delay_Measurement.py&rsquo; script. This will return the value in ps for the &lsquo;Path Delay&rsquo; in the next step. This file is located in the install folder for the TES C:\Program Files\Analog Devices\ADRV9001 Transceiver Evaluation Software\Examples\Python

Figure 5. Python Script Window 
 
 In the Board Configuration tab select the external loopback on the channel that will be performing DPD. Input the peak power and the calibrated path delay.

Figure 6. Board Configuration 
 
 In the Digital Pre-Distortion section of the Advanced Features tab the user can now enable the DPD on the channel of choice. There are options to select the Look Up Table size (larger number of entries provides more granularity) 
 
 The Pre-LUT Scale can be used to get better DPD performance if the input signal to the DPD block is too small. The default value is 2 and be changed from 0 to 3.75 in 0.25 steps. 
 The polynomial terms can be set to Default or when further optimising the user can custom tune the Taps for a better response. For now, we use the default setting. 
 
 Figure 7. Advanced Features (DPD) 
 
 In the Digital Pre-Distortion tab, the channel enabled in the Advanced features tab above will also appear enabled here. This tab gives the user the option to increase or decrease the number of samples of real data used to calculate the coefficients. There is an additional power scale that can be used for small input signals. 
 
 DPD Activation can be used to prevent the DPD from going unstable if the signal level going to the DPD block drops unexpectedly. For now, these settings can be left as the default values. 
 
 Figure 8. Digital Pre-Distortion Tab 
 
 The part can now be Programmed. Enabling the DPD will require a DPD tracking calibration which looks for a feedback signal. If the hardware setup is not set up correctly the device will fail to program.
 
 Note : In TES version 0.21.0 the DPD updates the coefficients at the start of a frame. If you are using the Automated TDD function the frame length is known and will occur frequently compared to operating in normal mode. In normal mode you will need to Stop and Start the Tx transmitting to trigger a frame and update the DPD coefficients. 
 Note : Make sure that the Transmit file being used has no discontinuities between the start and end of the file. The file is being sent in a loop and discontinuities will cause some unwanted spurious that will make destabilise the DPD performance.

Measurement Results 
 Doing the same measurement with and without DPD is the best way to show the impact. To run without DPD you will need to reset the part, disable DPD and program the part again. The results from this measurement are shown in Figure 9. The yellow trace is the result before the DPD is used and the pink trace is with DPD enabled. This shows a 16dB improvement however all setups with differing PAs will produce different results. Figure 9 is for illustrative purposes only.

Figure 9. Signal Analyser Measurement Example Measurement 
 The measurements below were taken using the ADRV9002 customer evaluation board controlled by the Transceiver Evaluation Software. The measurements show the results from two different PAs with DPD and without. 
 Measurement 1 - Tetra1 
 PA: Sky65160-11 
 ADRV9002 Profile: 
 
 Tetra1, 144Ksps 
 Internal LO 
 Tx Continuous On 
 
 Transmit Waveform: 
 
 TETRA1_sample_rate_144K_bw_25K
 
 This can be found in \ADRV9001 Transceiver Evaluation Software\Examples\Tx Data\

PAR is about 3dB

Figure 10: Measurement 1 - Tetra1 
 Measurement 2 - LTE10M 
 PA: Sky66297-11 
 ADRV9002 Profile: 
 
 TDD LTE10, 15.36Msps 
 Internal LO 
 Tx Continuous On 
 
 Transmit Waveform: 
 
 CFR_sample_rate_15p36M_bw_10M
 
 This can be found in \ADRV9001 Transceiver Evaluation Software\Examples\Tx Data\

PAR is about 9dB

Figure 11: Measurement 2 - LTE10M 
 Measurement 3 - LTE20M 
 PA: Sky66297-11 
 ADRV9002 Profile: 
 
 TDD LTE20, 15.36Msps 
 Internal LO 
 Tx Continuous On 
 
 Transmit Waveform: 
 
 CFR_sample_rate_15p36M_bw_10M
 
 This can be found in \ADRV9001 Transceiver Evaluation Software\Examples\Tx Data\

PAR is about 9dB

Figure 12: Measurement 3 - LTE20M 
 
 MATLAB DPD Analysis Tool 
 The MATLAB tool is aimed at analyzing the captured data from dpd_capture.py . This is an IronPython script that can be run from the TES to capture Tx and Rx data for analysis. This tool will help check signal integrity, signal alignment, PA compression level and at last the fine tuning of DPD. 
 
 Figure 13: MATLAB DPD analysis tool 
 This DPD analysis tool takes in a .csv file that is gererated in the TES with the dpd_capture.py script. This is run from the Python editor in the View tab. 
 
 Figure 14: Python Editor 
 For more in depth understanding of the DPD features and setup have a look at the whitepaper on The Complete Guide to Troubleshoot and Fine Tune Digital Predistortion 
 Running this will require a MATLAB runtime engine and this is included in the install package for the DPD Analyser. 
 The ADRV9002_DPD_Analyser can be downloaded here: ADRV9002_DPD_Analyser.zip 
 The dpd_capture.py file can be downloaded here: dpd_capture.zip 
 DPD Power Consumption 
 The ADRV9002's DPD power consumption, while seemingly dominated by the Observation Receiver (ORx), is actually primarily attributed to the DPD Actuator in average power calculations. This is because the ORx, despite consuming around 225mW for Tetra and 281mW for LTE 20 1T/1R during operation, only runs periodically for data capture (approximately every 2 seconds). The capture duration itself is short, ranging from tens of microseconds to several milliseconds depending on the profile: around 7.1ms for Tetra and 23&micro;s for LTE 20. 
 Therefore, the average ORx power consumption is significantly lower: around 0.8mW for Tetra and a mere 0.003mW for LTE 20 1T1R. This is calculated by multiplying the ORx power consumption with the ratio of data capture time to the period. Consequently, the ADRV9002's average DPD power consumption is mainly determined by the always-on Actuator, resulting in less than 3mW for Tetra, less than 18mW for LTE 20 1T, and less than 36mW for LTE 20 2T. More details on DPD power consumption are provided here: 
 PDF 
 DPD Performance Reports 
 The ADRV9001 employs DPD system similar to that of the AD9371 and AD9375 transceivers. The published performance reports for these transceivers with various PAs are listed below. Comparable DPD performance can be expected with the ADRV9001 using similar PAs, provided the instantaneous bandwidth (iBW) requirements are met. 
 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-HTN7G21P160H_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-HTN7G21P160H_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-NXP_20D025_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-NXP_20D025_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-RFPD-DE705_SP0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-Skyworks_SKY66297_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-Skyworks_SKY66292_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-Skyworks_SKY66295-11_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-Skyworks_SKY66296-11_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-Skyworks_SKY66288-11_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-Skyworks_SKY66294-11_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/DPD-PA-Test-Report-Skyworks_SKY66293-21_Sp0.pdf 
 https://www.analog.com/media/en/technical-documentation/test-reports/Skyworks_Tested_PA_SKY66394-11_5V_25C_R0.1.pdf

Question 3

Analog and Half-Band Peak Detectors

Accepted Answer

Introduction 
 This section describes how a signal is processed by a Transimpedance Amplifier (TIA) , Analog-to-Digital Converter (ADC), and Half-Band filter (HB), and how this affects the triggering of analog and HB peak detectors. 
 
 Figure 1. ADRV9001 Rx Chain 
 
 Figure 2. ADRV9001 Rx Chain and Frequency Response 
 Figures 1 and 2 illustrate the receiving (Rx) chain of a system. Figure 1 provides a block diagram overview, while Figure 2 details the signal's journey through key components showcasing the working of peak detectors. As shown in Figure 2, the input signal, at a frequency equal to the Radio Frequency (RF) carrier plus the Intermediate Frequency (IF), is first processed by an analog mixer. This mixer shifts the signal down to the IF by combining it with a Local Oscillator (LO) signal matching the RF carrier. The resulting IF signal is then passed through the TIA, converting it from a current to a voltage suitable for the ADC. One must note that the TIA frequency response is like that of an LPF, which also attenuates signals outside the band of interes t. Then this signal is passed through the LPF which further attenuates the out-of-band signals. The user can configure the LPF within TES as shown in Figure 3. 
 
 Figure 3. LPF Configuration 
 The ADRV9002 offers selectable LPF orders: 
 
 First-order: Reduces power consumption but provides lower image rejection. 
 Second-order: Improves image rejection but increases power consumption. 
 
 Figure 4 illustrates the frequency response of both first and second-order LPFs. This information is also available in the user guide. The LPF primarily serves to prevent aliasing and is not intended as a substitute for external signal filtering. 
 
 Figure 4. RX LPF Frequency Response at Different f1db Configuration 
 Before the ADC an Analog Peak Detector (APD) is placed for monitoring the peak power of the signal entering the ADC. Here the APD monitors the signal peak power; once the signal is above the certain threshold value provided by the user, this results in a flag in the gain control block. Then ADC digitizes the signal for further processing. This digitized signal is passed through the Half-Band (HB) filter and at this stage the HB peak detector monitors the signal, which may again result in a flag in the gain control block. The gain control block (see Figure 1) uses a combination of the APD upper threshold and the HB peak detector upper threshold to decide the level by which the attenuation will be adjusted in the front-end attenuator block. The peak detector configuration can be done in TES as shown in Figure 5. ADRV9002 has the flexibility to control the external gain block as well. 
 
 Figure 5. Peak Detector Configuration 
 The HB filtering is determined by the system clock rate ((&plusmn; 25*(System Clock))/184.32 MHz) and the system clock rate is depended on the profile. The frequency response of the filter is not given in the user guide. Instead, it is provided in a separate file: hb1.mat. The Figure 6 shows the filter magnitude response of HB filter for system clock of 150 MHz, 184.32 MHz and 200 MHz. 
 
 Figure 6. HB Filter Magnitude Response 
 Steps for Obtaining the HB Filter response using hb1.mat 
 
 Load the file using the MATLAB Command: load('hb1.mat'). 
 We will see a set of data as shown in Figure 7.

Figure 7. hb1.mat Data 
 
 The filter coefficients are stored in decflt_h. 
 Now use the function fvtool(decflt_h) to get the filter response. The filter response looks as shown in Figure 8.

Figure 8. Normalized Frequency Filter Magnitude Response

In the filter visualization tool, we see two options: one is analysis parameters and the other is sampling frequency as shown in Figure 9. 
 
 Figure 9. Filter Visualization Tool Options 
 
 In the Analysis parameters, we can change the plot axis as shown below. In this case, the normalize frequency option will be unchecked

Figure 10. Analysis Parameter 
 
 Once the above parameters are set, click on sampling frequency option and change the sampling frequency (Fs) to the system clock frequency (in this case, 184.32 MHz). The passband frequency is 25 MHz.

Figure 11. System Clock Rate 
 
 The below figure shows the filter response

Figure 12. Filter Magnitude Response for System Clock Rate of 184.32 MHz 
 Please find the hb1.mat file. 
 hb1.zip

Question 4

Implement an External LNA in TES

Accepted Answer

Background 
 The Rx gain table is a table of gain values that are used to control the gain of the receiver chain of ADRV9001. The table is generated by the Transceiver Evaluation Software (TES) based on the selected settings in the program. Using the gain indices from the table, the ADRV9001 gain can be set manually via API, pin or set automatically using Automatic Gain Control (AGC) system. The external LNA itself can then be controlled by the device&rsquo;s AGPIO output, based on the values generated in the gain table. The gain table contains values from 255 to 187, with 255 having 0 dB of gain with the lowest gain index containing the maximum gain of &ndash;30 dB. Every gain step is 0.5 dB of attenuation. Adding an external Low Noise Amplifier, for example a 14 dB LNA, the maximum total gain can be increased past the &ndash;30 dB limit of ADRV9001. Using that 14 dB LNA, we can have a total gain of &ndash;44 dB. See image of a simplified example version of a gain table below. On the left table, that is the maximum gain that ADRV9001 can produce, without using any external components. The right table shows a gain table when introducing external 14 dB gain LNA. The maximum gain increases to &ndash;44 dB. 
 
 Figure 1: simplified example version of a gain table 
 However, introducing an external component introduces different things to consider and keep in mind such as gain delays when switching from no external gain to having external gain, which in some cases, can take up to microseconds. 
 In the case of this guide, the receiver gain table used the LNA at 0 dB gain (bypass in this case) for gain indices from 255 to 195 and sets the external gain control to 0. When the gain entries are less than 195, the Low-Noise Amplifier (LNA) is adjusted to a gain of -14 dB, corresponding to gain table index 195, which itself corresponds to a gain of -30 dB. The subsequent gain index, 194, corresponds to a total gain of -30.5 dB, with an additional 14 dB gain from an external LNA. Consequently, the ADRV9001 gain becomes -16.5 dB. 
 
 Example Implementation 
 For this guide, an example of the ADL8111 bypass Low Noise Amplifier (LNA) was used to provide 12.5 (&plusmn; 1.5dB) gain and 0dB gain. To provide the switching between internal bypass mode and amplifier mode, an external circuit was created that lets an AGPIO pin control the state of the LNA, as required for the gain table. 
 1) Connect your signal generator to the LNA input and connect the LNA output to &ldquo;RX1A_IN&rdquo; on your ADRV9001 Evaluation Board. 
 2) In TES go to the &ldquo;Configure&rdquo; tab and select &ldquo;Board Configuration,&rdquo; scroll to the bottom and select the checkbox &ldquo;External LNA Gain Control&rdquo;. 
 
 Figure 2: External LNA settings from TES 
 AGPIOs for the external gain control, are assigned in groups of 4 as they share a single source control between them. Two bits (nibble) are used for each Rx, i.e. two bits for Rx1 and two bits for Rx2. So, AGPIO_0 to AGPIO_3 share a single source control, AGPIO_4 to AGPIO_7 share a single source control, and so on. In this case, only one AGPIO is used as there are only 2 gain steps, so a 1 or a 0 is written to only one AGPIO. 
 3) AGPIO_4 was arbitrarily used in this example, so &ldquo;Nibble 07-04&rdquo; is selected, as it contains the number of our selected AGPIO. Select &ldquo;Rx1 lower crumb/Rx2 upper crumb&rdquo; so the signal is at the lower GPIO pin, AGPIO_4 in this case, rather than AGPIO_7. The AGPIO is used to control the external LNA gain. In this case, toggling AGPIO_4 &lsquo;high&rsquo; turns the LNA off and setting the AGPIO &lsquo;low&rsquo; turns the external LNA on. 
 4) The settling delay and the LNA digital gain delay are described in the &lsquo;External LNA Timing&rsquo; section. Initially, these can be set to 0. 
 5) ADRV9001 can also support up to 3 different LNA&rsquo;s. Each LNA can provide any gain up to 29 dB, which is the maximum ADRV9001 can support. This allows a maximum gain of -117 dB to be achieved using 3x 29 dB LNA&rsquo;s and ADRV9001. More than a single LNA can be selected in the &ldquo;LNA Type&rdquo; dropdown box. The purpose of using multiple LNA&rsquo;s is to allow higher overall gain without compromising the ability to keep 0.5 dB step sizes. 
 As can be seen from the illustration below, there are 3 LNA&rsquo;s that either have a gain of 0 or -29 dB, and ADRV9001, which can support any value in 0.5 dB steps in the range of 0 dB to -30 dB. For example, to get -69 dB of total gain, 2 of the 3 LNA&rsquo;s need to be set to -29 dB, one LNA set to 0dB, and add -11 dB of gain from ADRV9001. To get -7.5 dB of gain, all LNAs need to be turned off, and ADRV9001 must provide &ndash;7.5 dB of gain. Other examples can be seen in the picture below. 
 
 Figure 3: Example LNA lineup 
 6) In this case, &ldquo;LNA Type&rdquo; was set to single and the &ldquo;Number of LNA Gain Steps&rdquo; was set to 2 as our system has two gain steps: 0 dB and 12.5 dB gain. Hence, 14000 mdB was entered in the &ldquo;LNA Gain Steps&rdquo; as the LNA had a small offset of about 1.5dB. Enter the gain of your external LNA in the corresponding step box, TES only accepts gain in 0.5 dB steps. ADRV9001 can support up to 4 gain steps total, with each step containing an extra integer multiple of 0.5 dB, as can be seen below, taken from the &ldquo;Receiver Datapath&rdquo; section in the &ldquo;Receiver Gain Control&rdquo; chapter in the User Guide. 
 
 Figure 4: Explanation of LNA control words from user guide 
 7) Select &ldquo;Program&rdquo; at the top menu and wait until it says &ldquo;Programmed&rdquo; on bottom right of the TES. Ensure that signal generator output is off during programming. 
 8) You can check if your settings were applied by going to the &ldquo;Gain Control&rdquo; tab and scrolling down to the gain table. The gain table is automatically generated based on the selected LNA settings from steps 3-5 in this guide. Your gain index values of 194 and lower should contain a &ldquo;1&rdquo; in the External Gain Control field. 
 
 Figure 5: Generated gain table 
 9) Now go to &ldquo;Receive&rdquo; tab and press play and turn on your signal generator. The signal should be seen on the spectrum. There is also an option called &ldquo;Interface Gain&rdquo; which can be applied to avoid saturating the signal due to the limitation of the bit-width of the data port. 
 
 Figure 6: Interface gain screenshot 
 Also, see Enhanced SSI In TES - Documents - TES GUI & Software Support ADRV9001 &ndash; ADRV9007 - EngineerZone (analog.com) to view gain index in real time. 
 10) Lower your &ldquo;Rx Gain (Index)&rdquo; until 195, and when you lower it one more time, the LNA will turn off if everything was configured correctly, and there should be a smooth, continuous drop of 0.5 dB. If the signal jumps or lowers dramatically, tweak the &ldquo;LNA Gain steps&rdquo; in 500mdB steps, back in &ldquo;Board Configuration&rdquo;, to ensure a continuous transition. An example of a smooth step of approximately 0.5 dB can be seen below, with the first picture containing the spectrum at gain index 195, and the second picture the index is lowered to 194, to power on the LNA. As can be seen, it's approximately 0.5 dB difference, meaning it is a smooth transition.

Figure 7: Rx Signal at Gain Index 195 
 
 Figure 8: Rx Signal at Gain Index 194 
 External LNA Timing 
 External LNA timing can be controlled directly by ADRV9002 for enabling LNA output power and LNA gain change timings. Figure 9 shows the external LNA timing for an example Rx frame. Delays are used to compensate for path delay latency to ensure timings of the external LNA are aligned with ADRV9002. These delays are described fully in the following sections. Note that there is a distinction between &lsquo;AGC Settling Delay&rsquo;/&rsquo;Digital Gain Delay&rsquo; and &lsquo;LNA AGC Settling Delay&rsquo;/&rsquo;LNA Digital gain delay&rsquo; as these cases are managed differently. 
 
 Figure 9: LNA Signals Timing Diagram 
 1) Timing of LNA output power 
 ADRV9002 AGPIOs can be used to enable LNA output power timings. For LNAs connected to Rx1, AGPIO1 is used and for Rx2, AGPIO9 is used. The AGPIOs corresponding to each channel are not user configurable. Figure 10 shows enabling this option in TES, in the &lsquo;External LNA&rsquo; section. 
 
 Figure 10: External LNA output power settings 
 The timing for these AGPIOs is configured by the enablement delays. The LNA enablement timing refers to the &ldquo;Rx On (LNA Power Out)&rdquo; line of the diagram in Figure 9 and described fully in the &ldquo;TIMING PARAMETERS CONTROL&rdquo; section of the user guide. The AGPIO will trigger some time after the Rx Enable rising and falling edges as controlled by the &lsquo;Rise to On&rsquo; and &lsquo;Fall to Off&rsquo; delays, respectively. 
 The intention of this signal is to be used to power-on an LNA at the correct time to align with the Rx framing on air (as per Figure 9). 
 2) Timing of LNA Gain Change 
 Figure 1 shows an example Rx frame, with 2 sub frames. The gain update period aligns with the subframe boundaries. The gain change timing will behave differently when there is a change to the LNA gain and when there is no change to the LNA gain. 
 In this example, the first gain change, there is no change to the gain update period. The gain change will be delayed by the &lsquo;digital gain delay&rsquo; parameter which is configured internally. The &lsquo;AGC settling delay&rsquo; is controlled by user in the AGC settings (slowLoopSettlingDelay), the delay to start the next AGC measurement. 
 On the second gain change, there is an LNA gain change. The delays for this gain change are configured via the LNA settings as highlighted in Figure 11. 
 
 Figure 11: LNA delay settings 
 To allow time for the LNA to change gain and signal to propagate, an extra &lsquo;LNA Digital Gain Delay&rsquo; is included which is to be measured by the user. This delay is defined as the path delay between the LNA/External Gain and the ADRV9002 front-end attenuator as shown in Figure 12. Measure this by setting the &lsquo;LNA Digital Gain Delay&rsquo; to 0, triggering an LNA gain change and observing the delay in gain change of the Rx captured data. 
 
 Figure 12: Path delays block diagram 
 For similar reasons, an &lsquo;LNA Settling Delay&rsquo; is included for the AGC. This settling delay will override the settling delay set in AGC settings when there is an external LNA gain change. This delay is recommended to align with &lsquo;Digital Gain Delay&rsquo; + &lsquo;LNA Digital Gain Delay&rsquo; as shown in Figure 9 i.e. after the gain change has fully propagated through the Rx data path.

Popular Forums

Product Forums

Application Forums

Design Center Forums

Highlighted Webinar

Places

Libraries

Latest Webinars

Challenge Yourself!

What's Brewing

Places

Resources

Highlighted Blogs

Latest Blogs

ADI Blogs

Visit ContentZone

Featured Content

View Content By Industry

View Content By Technology

Device Configurations: FAQ