Hello,
Below is my TDD profle to achive Link-16 Hop speeds using LO Mux.
I have the PLL BW set to 1200 KHz, High power and Fast calibration. And set the Transition time and frame duration to as small as they can go.
Table Index to Loop Mode, Input Clock is 300 MHz, with the divider set to 8.
Below is my Link-16 Profile, this gives a dwell time of around 9 to 10 us and the spectrum analyser output.
I wanted to test the tranceiver to see if i could exceed Link-16 Speed.
Please see my TDD setup below:
This gives a dwell time of 6us, however exhibits some strange behaviour.
Below is a plot of the IQ data, you can better see the Magnitude and Frequency vs Time
This IQ plots seem to show that the PLL locks loses lock and then relocks before hopping again. What can be the cause of this?
1) Is Link-16 the hard limit?
2) Are these TDD profiles configured Correctly?
2) Is there anyway to reduce the 3us switching time? I understand the PLL essentially has to re-tune from 0 rather from the last frequency it was on, Why is this?
is there anything in the userguide that explains this that i can put into my report to explain the Hopping limitations in simpler terms?
Thank you
