ADRV9002 Dynamic frequency hopping

Hi team,

      Is there any update?

Thank you.

Hi Yamuna,

1. I can't answer questions specific to No-OS here. Questions about No-OS should be posed in the Microcontroller no-OS Drivers forum.

2. The implementation of the dynamic table loading API is specific to our evaluation platform. It will not work on custom hardware, which is why we steer customers to use the static table loading API instead. However, if you have access to low-level functionality of your SPI bus, you may be able to replicate the functionality of the dynamic table loading API on your system. The difference is that the static API accesses SPI through the HAL and sends out a series of SPI transactions to load the table, whereas the dynamic API bypasses the HAL by writing the information of the SPI transaction directly to FPGA memory and sends it out in a single SPI transaction. The amount of data sent is unchanged, but but by combining the data into a single transaction, you remove any delays that occur between the individual SPI transactions.

3. I don't fully understand your question. Can you rephrase it, or perhaps use a visual aid to show what you're trying to measure?

Kind Regards,
Michał

Hi M_Bugajski ,

   Thank you for the reply.

1. This issue is resolved. I used the same api which is used in static configuration. 

2. My doubt is how to reduce the hopping table loading time. 

3. How to know the hopping time for certain no.of frequencies? Eg: In 1 sec, how many no.of frequencies can be hopped?  

Thanks & Regards,

D. Yamuna

Hi Yamuna,

2. Each SPI transaction results in an overhead delay. I don't have the exact numbers here, but hypothetically, if the overhead for one SPI transaction is X ns, and the time to send the address and upload one byte is Y ns, then uploading N bytes in single transactions would take N * (X + Y). However, if you packed all of that information into a single transaction, then the time taken would be N * X + Y.

3. The ADRV9002 is capable of meeting Link-16 timing requirements. However, this is dependent on the configuration. For fastest hopping, you will need to use LO Mux mode.

Kind Regards,
Michał

Hi M_Bugajski 

     Thank you for the reply.

I didn't understand the answer fully. Could you please explain in detail? 

Thanks & Regards,

D. Yamuna

Hi Yamuna, 

I was able to achieve link-16 on the evaluation board. I recommend you use an external clock, I set mine to 300MHz at 0dB, Hop mode to LO MUX. I was able to achieve a dwell time of 9us with a switching time of 3us. 

Hi Yamuna,

Which answer do you not understand?

Kind Regards,
Michał

Hi M_Bugajski ,

  Thank you for the reply. We are also using lo mux real time process mode only.  I didn't answer the below answers. Could you explain in detail?

Each SPI transaction results in an overhead delay. I don't have the exact numbers here, but hypothetically, if the overhead for one SPI transaction is X ns, and the time to send the address and upload one byte is Y ns, then uploading N bytes in single transactions would take N * (X + Y). However, if you packed all of that information into a single transaction, then the time taken would be N * X + Y.

The ADRV9002 is capable of meeting Link-16 timing requirements. However, this is dependent on the configuration. For fastest hopping, you will need to use LO Mux mode.

Thanks & regards,

D. Yamuna.

Hi OliverMenders ,

       Thank you for the reply. We are using external clock for our board. But we didn't try link-16 on the board. Could you please how link-16 is related to frequency hopping loading time? How did you achieve that dwell time & switching time? Is there any reference for it? If it is there, please tell me the process to achieve that dwell time.

Thanks & regards,

D. Yamuna

Hi Yamuna, 

I was able to achive a 10 us dwell with the following TDD Setup.

Set PLL Bandwidth to 1200 KHz, calibrtion to fast and power to high

Hope this helps.