Analog Initial error

Hi John,

Could you please provide us more details like what are we trying to achieve here, which platform are you using such as TES/c/python so that it will help me to provide you with efficient solution.

Regards

Rahul 

Hi Rahul,

I am using the ZCU102 platform with the ADRV9002, and my goal is to design the HDL in a no-OS environment while using the C code generated by TES to control the ADRV9002 for transmission and reception.

I am using LVDS, and the pin bindings for the SSI and SPI interfaces reference the HDL constraints provided by ADI. Regarding the reset for the ADRV9002, I am unsure whether it should be RESET_TRX or GP_INT, so I am controlling both through AXI_GPIO for reset management.

Could you provide information about the functions of RESET_TRX and GP_INT?

Regards

John

Hi John,

As you can see from the figure which represents the connection between ADRV9001 and FPGA, shows the physical pins i.e., RESET and GP_INT (General Purpose Interrupts). 

The RESET pin is used for resetting the ADRV9001, it is done to make sure that the chip is in the safe state before the initializing the ADRV9001, whereas GPI_INT is for general purpose interrupt output signal. You can find more details on GP_INT API (adi_adrv9001_gpio_GpIntStatus_Get(),adi_adrv9001_gpio_GpIntMask_Set(), adi_adrv9001_gpio_GpIntMask_Get()) in the doxygen file

Regards

Rahul

Hi Rahul,

Thank you for your reply.I have two more questions.

Could you provide some debugging directions regarding the error codes I mentioned earlier?

I would like to ask about the purposes of these ports:

1. device_clk_in and dev_mcs_fpga are declared in the wrapper but not connected to the Block Design. Are they not needed?
2. What are the purposes of ref_clk, sm_fan_tach, vadj_err, platform_status, and tdd_sync?

Thanks

John

Hi John,

Please find the details below 

device_clk_in and dev_mcs_fpga handels the clocking and Multichip Synchronization (MCS) reset. It loops back to the adrv9001 ip, from dev_out_clk to dev_clk. Please have a look at MCS in our user guide for more details. sm_fan_tach connects the FPGA fan.

platform_status lights up the LED so you know it's on, vadj_error reads if there is a voltage value error

Since you are trying to design the HDL in a no-OS environment, I will move this question to non-OS forum for better guidance. 

Regards,

Rahul