ADRV9002
Recommended for New Designs
The ADRV9002 is a highly integrated RF transceiver that has dual-channel transmitters, dual-channel receivers, integrated synthesizers, and digital signal...
Datasheet
ADRV9002 on Analog.com
Hi Team,
As part of the SSI interface verification, we have verified the Rx interface using the adi_adrv9001_RxSsiTestModeCfg_t
feature. Both RAMP_16_BIT
and FIXED_PATTERN
are working fine without any issues.
After Rx validation, we started Tx validation using Tx loopback to Rx.
In this Tx loopback test, we observed that the Tx data is getting left shifted by 1 bit, and the 16th bit is seen on the LSB (it’s like a rotate shift left).
For example:
0x8000
is transmitted on both I and Q. When captured at the receiver side with loopback, the data seen is 0x0001
.0x0010
, and at the receiver, it’s seen as 0x0020
. It’s always a 1-bit rotate shift left.What could be the issue causing this behavior?
Regards,
Siva.
Dorant - Moved from RF and Microwave to TES GUI & Software Support ADRV9001 – ADRV9007. Post date updated from Wednesday, August 14, 2024 11:05 AM UTC to Wednesday, August 14, 2024 2:54 PM UTC to reflect the move.
Hi,
we will get back to you.
Regards
Rahul
Hi RahulMushini ,
Can you please provide an update on this!
Hi Tushar,
I would like to know what is the platform are you using for connecting to ADRV9001 is it TES or Linux? As mentioned in the in the post : Tx SSI tuning issue? , could you try to clear or reset SERDES on the FPGA. It can be the case where the clk being fed to the FPGA from ADRV9002 causes a hiccup in the strobe alignment. Another thing to you can do if your platform has the ability to experiment with the Clk delay within ''adi_fpga9001_SsiCalibrationCfg_t *ssiCalibration''
Regards,
Rahul
Hi RahulMushini ,
We are using custom Artix-200T FPGA for connecting to ADRV9002.
We are using RX clock derived from the RX interface for the TX path as well by enabling the attribute "USE_RX_CLK_FOR_TX = 1".
Along with this for sending a constant value 0x8000 on the transmitter we had probed the strobe_p and idata_p lines as well. the image is attached. Please let us know if this not how it should be going. (yellow - Strobe_p and blue- IData_p)
The capture was taken from the output of FPGA and just before it reaches the ADRV9002.
As for the resetting the SERDES, yes we can try resetting the SERDES once again in order to verify the hiccup.
Regards,
Tushar
Hi Tushar,
Can you have a look at the hardware software selection guide below (https://www.analog.com/media/en/evaluation-boards-kits/evaluation-software/adrv9001_software_and_hardware_selection_guide.pdf?isDownload=true) and let me know which one are you using Product Line SDK package or Open Source, Linux based, Prototyping software. This will allow us to provide you better support.
Regards
Rahul
Hi Tushar,
I would like to know if you were successful resetting the SERDES on the FPGA for every test? Did you try to experiment with the calibration delays as suggested above?
If you still see the issue, could you replicate the problem in our provided platform so that we can replicate the same in our lab?
Regards
Rahul
Closing this issue due to inactivity.