Hello,
As the title says, during my recent product development I discovered the problem with Tx channel latency on my custom board with the ADRV9004 chip on it. I observe an additional, randomly changing Tx channel latency after recovering from sleep mode. It varies between 0 and 6 samples. Once the chip wakes up this value remains constant. However, after the first power up the latency is deterministic and always the same. I managed to connect the MCS signal from the chip to the FPGA although I hadn't considered this in my design, in the hope that it would help, but it seems that MCS synchronisation is only available after calibration and cannot be done later. My initial thought was that some output data would get stuck in the FPGA's FIFO after LSSI shuts down, but it seems that is not the case. What I now think is that the data is somehow stuck inside the ADRV9004 somewhere at the interpolation stage.
Could you please tell me if there is a way to keep the latency constant or at least to determine the additional latency value?
Kind regards,
bartk