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Multi-Chip Synchronization

Category: Hardware
Product Number: ADRV9003

I have some MCS-related questions:

1. I understand from UG-1828 Rev0 Fig. 84 that the MCS signal will be resampled in the ARDRV9003 by the DEV_CLK. From this it appears that the higher jitter on an MCS signal generated by an FPGA as opposed to an AD9528-type low-jitter clock chip will not have any negative effect on the multi-chip synchronization feature. Is this true?

2. I understand that if the MCS feature is not enabled, the latency of each ADRV9003 channel will not be the same. But after reset, will the latency of each channel at least remain fixed in this case until the next reset or until power down? Or would this hold true if the MCS feature is enabled but no MCS signal is applied?

3. Is there any delay specification for the ADRV9003 pin-L14 DEV_CLK_OUT output relative to the DEV_CLK_IN input?