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9002 register settings for DAC Channel RATE

Category: Hardware
Product Number: 9002

I am using the adrv9002 and have something running but i do not think i have a good configuration for DACs.

I used TES to generate the code to give me 20Msps.

I use the API for the spi portion of configuration.

I am manually configuring the FPGA9001 portion.

I have a question on the clock registers for the DAC on the following:

0x004c REG_RATECNTRL DAC   is read write

0x0054 REG_STATUS1  read only

0x0058 REG_STATUS2 read only

I am using the info from here

What am i supposed to read for registers 0x0054 REG_STATUS1 ?

I am getting 0x0.

For the clock rato 0x0058 REG_STATUS2 i am getting 4.

What would i set 0x004c REG_RATECNTRL DAC  to?

The description says "The effective dac rate (the maximum possible rate is dependent on the interface clock). The samples are generated at 1/RATE of the interface clock. "

I am running from a Zedboard with so i the clock is 100MHz.

Would i set the RateCntl to 5 so i get 100 / 5 = 20 Msps?

My TES config is for 20 Msps using DDR CMOS 4 lanes.